| Alternate document: Details Exploiting Locality for Low-Power Design (96) Renu Mehra, Lisa Guerra, Jan Rabaey |
Renu Mehra and Jan Rabaey Department of Electrical Engineering and Computer...  Home/Search
Context Related
Links: ACM DBLP | berkeley.edu/~renu/papers/iccad96.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: berkeley.edu/~renu/work (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized designs, about 10 to 40% of the total power may be dissipated in buses, multiplexors, and drivers. We present a novel approach targeted at the reduction of power dissipation in interconnect elements --- buses, multiplexors, and buffers. The scheduling, assignment, and allocation techniques presented in this paper exploit the... (Update)
Context of citations to this paper: More
.... have demonstrated that in chip designs, about 10 to 40 of the total power may be dissipated in buses, multiplexers and drivers [47]. This amount can increase dramatically for systems with multiple chips due to large off chip bus capacitance. The amount of energy...
.... scheduling [15] reduction of data path complexity and improved design quality [16] system level partitioning [17] and power reduction [18]. Rao and Kurdahi [17] discussed template generation for clustering (at the system level) using the first fit bin filling heuristic....
Cited by: More
Behavioral Level Guidance Using Property-Based Design.. - Lisa Marie Guerra (1996) (Correct)
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997) (Correct)
Instruction Generation and Regularity Extraction.. - Brisk, Kaplan.. (2002) (Correct)
Active bibliography (related documents): More All
0.5: Concurrent Algorithm Development and Software.. - Kirovski, Potkonjak (Correct)
0.5: A Technique for Avoiding Isomorphic Netlists in.. - Marwedel.. (1996) (Correct)
0.2: Shared Buffer Implementations of Signal Processing Systems .. - Murthy, Bhattacharyya (2001) (Correct)
Similar documents based on text: More All
0.3: Exploiting Locality for Low-Power Design - Mehra, Guerra, Rabaey (1996) (Correct)
0.2: Low-Power Architectural Synthesis and the Impact of.. - Mehra, Guerra, Rabaey (1996) (Correct)
0.2: List of Slides - Switching And Multiplexing (Correct)
Related documents from co-citation: More All
10: Optimizing Power Using Transformations - Chandrakasan, Potkonjak et al. - 1995
9: Behavioral Synthesis for Low-Power (context) - Raghunathan, Jha - 1994
7: A Portable Multimedia Terminal (context) - Sheng, Chandrakasan et al. - 1992
BibTeX entry: (Update)
Mehra R., Rabaey J.: "Exploiting regularity for low-power design", proceedings of the international Conference on computer-aided design, 1996. http://citeseer.ist.psu.edu/mehra96exploiting.html More
@inproceedings{ mehra96exploiting,
author = "Renu Mehra and Jan M. Rabaey",
title = "Exploiting regularity for low-power design",
booktitle = "{ICCAD}",
pages = "166-172",
year = "1996",
url = "citeseer.ist.psu.edu/mehra96exploiting.html" }
Citations (may not include all citations):151 Force-Directed Scheduling for Behavioral Synthesis of ASIC's (context) - Paulin, Knight - 1989
114 Fast Prototyping of Datapath-Intensive Architectures (context) - Rabaey, Chu et al. - 1991 ACM
65 Architectural Power Analysis: The Dual Bit Type Method (context) - Landman, Rabaey - 1995
36 Behavioral Level Power Estimation and Exploration - Mehra, Rabaey - 1994
19 Greed is Good: Approximating Independent Sets in Sparse and .. (context) - Halldorsson, Radhakrishnan - 1994 DBLP
13 System-level Design Guidance using Algorithm Properties (context) - Guerra, Potkonjak et al. - 1994
13 Low Power Architectural Synthesis and the Impact of Exploiti.. - Mehra, Guerra et al. - 1996
7 Instruction set mapping for performance optimization (context) - Corazao, Khalaf et al. - 1993 ACM
5 An Approach to Scheduling and Allocation using Regularity Ex.. (context) - Rao, Kurdahi - 1993
2 Re-evaluating the Design Space for Register-Transfer Level H.. (context) - McFarland - 1987
2 New Methods for Coloring and Clique Partitioning in Data Pat.. (context) - Springer, Thomas - 1991 ACM
1 Module Assignment and Interconnect Sharing of Pipelined data.. (context) - Park, Kurdahi - 1989
1 Synthesis of Accelerator Data Paths for High-Throughput Sign.. (context) - Geurtz - 1995
1 Evaluating Layout Area Tradeoffs for high level synthesis ap.. (context) - Kurdahi, Ramachandran - 1993
1 Possibilities of deep-submicrometer CMOS for very-highspeed .. (context) - Masaki - 1993
1 Asymtotically Trivial Global Routing: A Stochastic Analysis (context) - Sorkin - 1987
1 Interconnect Optimization for Multiprocessor Architectures (context) - Stok - 1990
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://infopad.eecs.berkeley.edu/~renu/work.html): More
Optimizing Power Using Transformations - Chandrakasan, Potkonjak, Mehra.. (1995) (Correct)
Low-Power Architectural Synthesis and the Impact of.. - Mehra, Guerra, Rabaey (1996) (Correct)
Design Guidance In The Power Dimension - Rabaey, Guerra, Mehra (1995) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC