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Abstract: System-chip design which starts at the RTL-level today has hit a plateau of productivity and re-use which can be characterised as a "Silicon Ceiling". Breaking through this plateau and moving to higher and more effective re-use of IP blocks and system-chip architectures demands a move to a new methodology: one in which the best aspects of today's RTL based methods are retained, but complemented by new levels of abstraction and the commensurate tools to allow designers to exploit the... (Update)
Context of citations to this paper: More
...per block function requires significant RT coding overhead. This situation has been recognized by other authors as a Silicon Ceiling [7]. Research solutions have been either to encapsulate VHDL within an advanced design environment [6] or else to extend the semantics of VHDL...
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BibTeX entry: (Update)
G. Martin. Design methodologies for system level ip. In Proc. DATE 1998, pages 286--302. http://citeseer.ist.psu.edu/martin98design.html More
@misc{ martin98design,
author = "G. Martin",
title = "Design methodologies for system level ip",
text = "G. Martin. Design methodologies for system level ip. In Proc. DATE 1998,
pages 286--302.",
year = "1998",
url = "citeseer.ist.psu.edu/martin98design.html" }
Citations (may not include all citations):73 Interface-based design (context) - Rowson, Sangiovanni-Vincentelli - 1997
15 Hardware-Software Co-Design of Embedded Systems (context) - Balarin, Chiodo et al. - 1997
11 Methodology and Technology for Design of Communications and .. (context) - Martin, Salefski - 1998
6 Blocking in a system on a chip (context) - Hunt, Rowson - 1996
1 Gary Smith notes that designers in Japan as of January 1997 .. (context) - Smith, Private et al. - 1997
1 See VSI web site URL httpwww (context) - Alliance, VSI et al. - 1997
1 HW-SW Co-Design: A Perspective (context) - Martin - 1997
1 Virtual prototyping (context) - Rowson - 1997
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