Milo M. Martin, Amir Roth, Charles N. Fischer  Home/Search
Context Related
| davinci.snu.ac.kr/link...martin97.ps.gz cardit.et.tudelft.nl/~...martin97.ps.gz wisc.edu/~fischer/deadvalues.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: davinci.snu.ac.kr/links/ilp/ (more) From: 128.105.7.11/~fischer/ (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI provides assertions that certain register values are dead, meaning they will not be read before being overwritten. The processor can use DVI to track dead registers and dynamically eliminate unnecessary save and restore instructions from the execution stream at procedure calls and context switches. Our results indicate that dynamic saves and restore instances can be reduced by 46% for procedure... (Update)
Cited by: More
Design and Applications of a Virtual Context Architecture - Oehmke, Binkert.. (2004) (Correct)
Dynamically Reducing Pressure on the Physical.. - Tran, Nelson.. (2004) (Correct)
Physical Register Inlining - Lipasti, Mestan, Gunadi (2004) (Correct)
Active bibliography (related documents): More All
0.5: Process Migration on Chorus - O'Connor (Correct)
0.2: The Named-State Register File - Nuth (1993) (Correct)
0.2: The Named-State Register File: Implementation and Performance - Peter Nuth (1995) (Correct)
Similar documents based on text: More All
0.6: TkDVI: DVI Previewing with Tcl and Tk - Application-Level Scripting Is (Correct)
0.2: A Device Independent DVI Interpreter Library for.. - Hirotsugu Kakugawa.. (2000) (Correct)
0.2: Light Weight Optimizations for Reducing Hot Saves and.. - Of Callee-Saved Registers (Correct)
Related documents from co-citation: More All
10: superscalar microprocessor (context) - Yeager - 1996
7: Exploiting short-lived variables in superscalar processors (context) - Lozano, Gao - 1995
6: Multiple-banked register file architectures (context) - Cruz, Gonzlez et al. - 2000
BibTeX entry: (Update)
M. Martin, A. Roth, and C. Fischer. Exploiting dead value information. In 30th International Symposium on Microarchitecture, pages 125--135, December 1997. http://citeseer.ist.psu.edu/martin97exploiting.html More
@inproceedings{ martin97exploiting,
author = "Milo M. Martin and Amir Roth and Charles N. Fischer",
title = "Exploiting Dead Value Information",
booktitle = "International Symposium on Microarchitecture",
pages = "125-135",
year = "1997",
url = "citeseer.ist.psu.edu/martin97exploiting.html" }
Citations (may not include all citations):118 The interaction of architecture and operating system design - Anderson, Levy et al. - 1991
99 Global register allocation at link time - Wall - 1989
94 The effect of context switches on cache performance (context) - Mogul, Borg - 1991
79 Computer Sciences Department (context) - Burger, Austin et al. - 1997
54 Digital 21264 sets new standard (context) - Gwennap - 1996
39 Memory-System Design Considerations for Dynamically-Schedule.. - Farkas - 1997
35 Register file design considerations in dynamically scheduled.. - Farkas, Jouppi et al. - 1996
28 Register traffic analysis for streamlining inter-operation c.. - Franklin, Sohi - 1992
22 Designing high-bandwidth on-chip caches (context) - Wilson, Olukotun - 1997
17 uses decoupled architecture (context) - Gwennap - 1994
16 Exploiting short-lived variables in superscalar processors (context) - Lozano, Guang et al. - 1995
15 An enhanced access and cycle time model for on-chip caches (context) - Jouppi, Wilton - 1994
11 Wholeprogram optimization for time and space efficient threa.. - Grunwald, Neves - 1996
7 Minimum cost interprocedural register allocation - Kurlander, Fischer - 1996
6 Crafting a Compiler with C (context) - Fischer, Jr - 1991
5 Architectural support for reduced register saving/restoring .. (context) - Huguet, Lang - 1991
2 VAX-11 Architecture Reference Manual (context) - Corporation - 1982
1 Multiscalar architectures (context) - Sohi, Breach et al. - 1995
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://davinci.snu.ac.kr/links/ilp/): More
Value Locality and Load Value Prediction - Lipasti, al. (1996) (Correct)
Multiscalar Processors - Sohi (1995) (Correct)
Memory Bandwidth Limitations of Future Microprocessors - Burger (1996) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC