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Abstract: In this paper we present a processor microarchitecture that can simultaneously execute multiple threads and has a clustered design for scalability purposes. A main feature of the proposed microarchitecture is its capability to spawn speculative threads from a single-thread application at run-time. These speculative threads use otherwise idle resources of the machine. Spawning a speculative threads involves predicting its control flow as well as its dependences with other threads and the values... (Update)
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0.4: A Quantitative Assessment of Thread-Level Speculation.. - Marcuello, González (1999) (Correct)
0.4: Value Prediction for Speculative Multithreaded.. - Marcuello, Tubella.. (1999) (Correct)
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BibTeX entry: (Update)
P. Marcuello and A. Gonzalez. Clustered Speculative Multithreaded Processors. In 13th International Conference on Supercomputing (ICS), June 1999. http://citeseer.ist.psu.edu/marcuello99clustered.html More
@inproceedings{ marcuello99clustered,
author = "Pedro Marcuello and Antonio Gonzalez",
title = "Clustered speculative multithreaded processors",
booktitle = "International Conference on Supercomputing",
pages = "365-372",
year = "1999",
url = "citeseer.ist.psu.edu/marcuello99clustered.html" }
Citations (may not include all citations):386 ATOM: A system for building customized program analysis tool.. (context) - Srivastava, Eustace - 1994
269 Multiscalar Processors - Sohi, Breach et al. - 1995
251 Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers et al. - 1995 DBLP
214 Combining Branch Predictors - McFarling - 1993
175 Complexity-Effective Superscalar Processor - Palacharla, Jouppi et al. - 1997
145 Exceeding the Dataflow Limit via Value Prediction - Lipasti, Shen - 1996 ACM DBLP
139 The Predictability of Data Values - Sazeides, Smith - 1997
125 Trace Processors - Rotemberg, Jacobson et al. - 1997 ACM DBLP
116 Highly Accurate Data Value Prediction Using Hybrid Predictor.. - Wang, Franklin - 1997 ACM DBLP
77 The Potential of Using Thread-Level Data Speculation to Faci.. - Steffan, Mowry - 1998
72 A Dynamic Multithreading Processor - Akkary, Driscoll - 1998 ACM DBLP
72 Data Speculation Support for a Chip Multiprocessor (context) - Hammond, Willey et al. - 1998 ACM DBLP
70 The Superthreaded Architecture: Thread Pipelining with Run-T.. - Tsai, Yew - 1996
70 The Expandable Split Window Paradigm for Exploiting Fine Gra.. - Franklin, Sohi - 1992
64 Memory Dependence prediction Using Store Sets - Chrysos, Emer - 1998
62 The Multicluster Architecture: Reducing Cycle Time Through P.. - Farkas, Chow et al. - 1997
61 Improving the Accuracy and performance of Memory Communicati.. - Tyson, Austin - 1997 ACM DBLP
60 Software and Hardware for Exploiting Speculative Parallelism.. - Oplinger - 1997
53 Improving Superscalar Instruction Dispatch and Issue by Expl.. - Vajapeyam, Mitra - 1997
49 Can Program Profiling Support Value Prediction - Gabbay, Mendelson - 1997
47 Disjoint Eager Execution. An Optimal Form of Speculative Exe.. - Uht, Sindagi - 1995
46 Streamlining Inter-operation Memory Communication via Data D.. (context) - Moshovos, Sohi - 1997
45 Threaded Multiple Path Execution - Wallace, Calder et al. - 1998 ACM DBLP
39 Path-Based Next Trace Prediction - Jacobson, Rotenberg et al. - 1997 ACM DBLP
26 Speculative Multithreaded Processors - Marcuello, Gonzalez et al. - 1998 ACM DBLP
26 Hardware and Software Support for Speculative Execution of S.. - Krishnan, Torrellas - 1998
25 Single-Program Speculative Multithreading (SPSM) Architectur.. (context) - Dubey, O'Brien et al. - 1995
21 PEWs: A Decentralized Dynamic Scheduler for ILP Processing (context) - Kemp, Franklin - 1996 DBLP
19 Coarse-Grained Speculative Execution in Shared-Memory Multip.. - Kazi, Lilja - 1998 ACM DBLP
15 Multithreaded Decoupled Architecture (context) - Dorojevets, Oklobdzija - 1995
15 Control Speculation in Multithreaded Processors through Dyna.. - Tubella, Gonzalez - 1998 ACM DBLP
10 Speculative Execution via Address Prediction and Data prefet.. - Gonzalez, Gonzalez - 1997
10 Control and Data Dependence Speculation in Multithreaded Pro.. (context) - Marcuello, Gonzalez
1 Digital 2264 Sets New Standard (context) - Gwennap - 1996
1 Trace Cache: a Low Latency Approach to High Bandwidth Instru.. (context) - Rotemberg, Bennet et al. - 1996 DBLP
1 Multipath Execution: Oportunities and Limits (context) - Ahuja, Skadron et al. - 1998
1 The Potencial of Data Value Speculation to Boost ILP (context) - Gonzalez, Gonzalez - 1998
1 Selective Dual Patch Execution (context) - Heil, Smith - 1996
1 Selective Eager Execuytion on the PolyPath Architecture (context) - Klauser, Paithankar et al. - 1998
1 Memory Address Predicition for Data Speculation (context) - Gonzalez, Gonzalez - 1997
1 The Performance Potencial of Data Dependence Speculation & C.. (context) - Sazeides, Vassiliadis et al. - 1996
1 Limits of Instruction Level Parallelism with Data Speculatio.. - Gonzalez, Gonzalez - 1998
1 Dynamic Speculation and Syncronization of Data Dependences (context) - Moshovos, Breach et al. - 1997
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