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Speculative Multithreaded Processors (1998)  (Make Corrections)  (26 citations)
Pedro Marcuello, Antonio González, Jordi Tubella
International Conference on Supercomputing



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Abstract: In this paper we present a novel processor microarchitecture that relieves four of the most important bottlenecks of superscalar processors to exploit instruction level parallelism: the serialization imposed by true dependences, the instruction window size, the complexity of a wide issue machine and the instruction fetch bandwidth requirements. The new microarchitecture executes simultaneously multiple threads of control obtained from a single program by means of control speculation techniques... (Update)

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18:   Multiscalar processors - Sohi, Breach et al. - 1995
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BibTeX entry:   (Update)

Pedro Marcuello, Antonio Gonzales, and Jordi Tubella. Speculative multithreaded processors. In Proceedings of the 1998 International Conference on Supercomputing, July 13 - 17, 1998. http://citeseer.ist.psu.edu/marcuello98speculative.html   More

@inproceedings{ marcuello98speculative,
    author = "Pedro Marcuello and Antonio Gonzalez and Jordi Tubella",
    title = "Speculative Multithreaded Processors",
    booktitle = "International Conference on Supercomputing",
    pages = "77-84",
    year = "1998",
    url = "citeseer.ist.psu.edu/marcuello98speculative.html" }
Citations (may not include all citations):
386   ATOM: A system for building customized program analysis tool.. (context) - Srivastava, Eustace - 1994
269   Multiscalar Processors - Sohi, Breach et al. - 1995
251   Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers et al. - 1995
230   Limits of Instruction-Level Parallelism - Wall - 1993
190   Value Locality and Load Value Prediction - Lipasti, Wilkerson et al. - 1996
183   Trace Cache: a Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Jacobson et al. - 1996
175   Complexity-Effective Superscalar Processors - Palacharla, Jouppi et al. - 1997
145   Exceeding the Dataflow Limit via Value Prediction - Lipasti, Shen - 1996
139   The Predictability of Data Values - Sazeides, Smith - 1997
125   Trace Processors - Rotenberg, Bennett et al. - 1997
116   Highly Accurate Data Value Prediction using Hybrid Predictor.. - Wang, Franklin - 1997
102   Dynamic Speculation and Synchronization of Data Dependences - Moshovos, Breach et al. - 1997
93   Optimization of Instruction Fetch Mechanism for High Issue r.. - Conte, Menezes et al. - 1995
81   Implementing Precise Interrupts in Pipelined Processors (context) - Smith, Pleszkun - 1988
75   Increasing the Instruction Fetch Rate via Multiple Branch Pr.. - Yeh, Marr et al. - 1993
75   Computer Architecture (context) - Hennessy, Patterson - 1996
70   A Performance Study of Software and Hardware Data Prefetchin.. (context) - Chen, Baer - 1994
70   The Superthreaded Architecture: Thread Pipelining with Run-T.. - Tsai, Yew - 1996
70   The Expandable Split Window Paradigm for Exploiting Fine Gra.. - Franklin, Sohi - 1992
67   ARB: A Hardware Mechanism for Dynamic Reordering of Memory R.. - Franklin, Sohi - 1996
61   Improving the Accuracy and Performance of Memory Communicati.. - Tyson, Austin - 1997
57   A Load Instruction Unit for Pipelined Processors (context) - Eickemeyer, Vassiliadis - 1993
53   Improving Superscalar Instruction Dispatch and Issue by Expl.. - Vajapeyam, Mitra - 1997
49   Can Program Profiling Support Value Prediction - Gabbay, Mendelson - 1997
49   The Performance Potential of Data Dependence Speculation & C.. - Sazeides, Vassiliadis et al. - 1996
46   Streamlining Inter-operation Memory Communication wia Data D.. (context) - Moshovos, Sohi - 1997
38   Zero-Cycle Loads: Microarchitecture Support for Reducing Loa.. - Austin, Sohi - 1995
29   Streamlining Data Cache Access with Fast Address Calculation - Austin, Pnevmastikatos et al. - 1995
26   Advanced Performance Features of the 64-bit PA-8000 (context) - Hunt - 1995
25   Single-Program Speculative Multithreading (SPSM) Architectur.. (context) - Dubey, O'Brien et al. - 1995
18   The Future of Microprocessors (context) - Yu
17   Concurrency Extraction via Hardware Methods Executing the St.. (context) - Uht - 1992
15   Multithreaded Decoupled Architecture (context) - Dorojevets, Oklobdzija - 1995
13   Hardware Support for Hiding Cache Latency - Golden, Mudge - 1993
10   Speculative Execution via Address Prediction and Data Prefet.. - Gonzalez, Gonzalez - 1997
7   Data Memory Alternatives for Multiscalar Processors - Breach, Vijaykumar et al. - 1997
5   Memory Address Prediction for Data Speculation (context) - Gonzalez, Gonzalez - 1997
2   Control Flow Prediction with Tree-like Graphs for Superscala.. (context) - Dutta, Franklin - 1995
1   Authors and title removed for anonimity (context) - title, anonimity et al. - 1998



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Multithreaded Decoupled Access/Execute Processors - Parcerisa, González (1997)   (Correct)
Data Speculative Multithreaded Architecture - González, Marcuello (1997)   (Correct)
Implementing PARMACS Macros for Shared Memory.. - Artiaga, Navarro, .. (1997)   (Correct)

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