(Enter summary)
Abstract: In this paper we present a novel processor microarchitecture that relieves four of the most important
bottlenecks of superscalar processors to exploit instruction level parallelism: the serialization imposed by
true dependences, the instruction window size, the complexity of a wide issue machine and the instruction
fetch bandwidth requirements. The new microarchitecture executes simultaneously multiple threads of
control obtained from a single program by means of control speculation techniques... (Update)
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BibTeX entry: (Update)
Pedro Marcuello, Antonio Gonzales, and Jordi Tubella. Speculative multithreaded processors. In Proceedings of the 1998 International Conference on Supercomputing, July 13 - 17, 1998. http://citeseer.ist.psu.edu/marcuello98speculative.html More
@inproceedings{ marcuello98speculative,
author = "Pedro Marcuello and Antonio Gonzalez and Jordi Tubella",
title = "Speculative Multithreaded Processors",
booktitle = "International Conference on Supercomputing",
pages = "77-84",
year = "1998",
url = "citeseer.ist.psu.edu/marcuello98speculative.html" }
Citations (may not include all citations):
386
ATOM: A system for building customized program analysis tool.. (context) - Srivastava, Eustace - 1994
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Limits of Instruction-Level Parallelism
- Wall - 1993
190
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183
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175
Complexity-Effective Superscalar Processors
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139
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Optimization of Instruction Fetch Mechanism for High Issue r..
- Conte, Menezes et al. - 1995
81
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53
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Multithreaded Decoupled Architecture (context) - Dorojevets, Oklobdzija - 1995
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10
Speculative Execution via Address Prediction and Data Prefet..
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7
Data Memory Alternatives for Multiscalar Processors
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5
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2
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Authors and title removed for anonimity (context) - title, anonimity et al. - 1998
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