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Abstract: High-level synthesis tools generate register-transfer level designs from algorithmic behavioral specifications. High-level synthesis process typically consists of dependency graph scheduling, functional unit allocation, register allocation, interconnect allocation and controller generation tasks. Widely used algorithms for these tasks retain the overall control flow structure of the behavioral specification allowing code motion only within basic blocks. Further, high-level synthesis algorithms... (Update)
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BibTeX entry: (Update)
@article{ mansouri00automated,
author = "Nazanin Mansouri and Ranga Vemuri",
title = "Automated Correctness Condition Generation for Formal Verification of Synthesized {RTL} Designs",
journal = "Formal Methods in System Design: An International Journal",
volume = "16",
number = "1",
month = "January",
publisher = "Kluwer Academic Publishers",
pages = "59--91",
year = "2000",
url = "citeseer.ist.psu.edu/mansouri99automated.html" }
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