See this document in CiteSeerX!

Precise Delay Generation Using Coupled Oscillators (1994)  (Make Corrections)  (31 citations)
John G. Maneatis



  Home/Search   Context   Related

 
View or download:
stanford.edu/group/../...jgm_thesis.pdf
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  stanford.edu/group/people (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: This thesis describes a new class of delay generation structures which can produce precise delays with sub-gate delay resolution. These structures are based on coupled ring oscillators which oscillate at the same frequency. One such structure, called an array oscillator, consists of a linear array of ring oscillators. A unique coupling arrangement forces the outputs of the ring oscillators to be uniformly offset in phase by a precise fraction of a buffer delay. This arrangement enables the... (Update)

Context of citations to this paper:   More

...set of discrete frequencies are sufficient for our needs and intended by design. In our implementation, a wide frequency range ICO is used [7]. This was chosen because of some nice tunability and sensitivity behaviors of the ICO. Shown in Fig. 6 are the details of the circuit....

Cited by:   More
The CMOS On-chip oscillator based on level Tracking Technique - Chang, Chen, Yang, Lee (2002)   (Correct)
Converters in 0.25-m CMOS - Analog Devices Inc   (Correct)
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11.. - Multiplier Clock..   (Correct)

Active bibliography (related documents):   More   All
3.9:   High Performance Inter-Chip Signalling - Sidiropoulos (1998)   (Correct)
1.3:   Design of High-Speed Serial Links in CMOS - Yang (1998)   (Correct)
0.9:   A 2-GHz 1.6-mW Phase-Locked Loop - Razavi (1997)   (Correct)

Similar documents based on text:   More   All
0.7:   Comparison And Analysis Of Phase Noise In Ring Oscillators - Liang Dai And (2000)   (Correct)
0.4:   Deadline Assignment To Reduce Output Jitter Of - Real-Time Tasks Taewoong (2000)   (Correct)
0.4:   Phase Noise in Multi-Gigahertz CMOS Ring Oscillators - Ali Hajimiri Sotirios (1998)   (Correct)

Related documents from co-citation:   More   All
12:   Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques (context) - Maneatis - 1996
11:   A Variable Delay Line PLL for CPU-Coprocessor Synchronization (context) - JOHNSON, HUDSON - 1988
8:   Transmission Lines for Digital and Communication Networks (context) - Richard - 1969

BibTeX entry:   (Update)

J. Maneatis, and M. Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE J. of Solid State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec 1993. http://citeseer.ist.psu.edu/maneatis94precise.html   More

@techreport{ maneatis94precise,
    author = "John George Maneatis",
    title = "Precise Delay Generation Using Coupled Oscillators",
    number = "CSL-TR-94-629",
    pages = "116",
    year = "1994",
    url = "citeseer.ist.psu.edu/maneatis94precise.html" }
Citations (may not include all citations):
63   Analysis and Design of Analog Integrated Circuits (context) - Gray, Meyer - 1984
44   Phaselock Techniques (context) - Gardner - 1979
23   A Variable Delay Line PLL for CPU-Coprocessor Synchronizatio.. (context) - Johnson, Hudson - 1988
18   Charge-Pump Phase-Lock Loops (context) - Gardner - 1980
15   A PLL Clock Generator with 5 to 110 MHz of Lock Range for Mi.. (context) - Young - 1992
13   Design of PLL-Based Clock Generation Circuits (context) - Jeong - 1987
8   Phase-Locked Loop Circuit Design (context) - Wolaver - 1991
8   Noise in Relaxation Oscillators (context) - Abidi, Meyer
7   Probability and Random Processes for Electrical Engineering (context) - Alberto - 1989
5   A Delay Line Loop for Frequency Synthesis of De-Skewed Clock (context) - Waizman
5   A 155-MHz Clock Recovery Delay- and PhaseLocked Loop (context) - Lee, Bulzacchelli - 1992
4   A 320MHz CMOS Triple 8b DAC with On-Chip PLL and Hardware Cu.. (context) - Reynolds
4   A Novel Precision MOS Synchronous Delay Line (context) - Bazes
4   A Monolithic 480Mb/s Parallel AGC/Decision/Clock-Recovery Ci.. (context) - Hu, Gray
3   Cell-Based Fully Integrated CMOS Frequency Synthesizers (context) - Mijuskovic
3   A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-u.. (context) - Kim - 1990
3   Phase-Locked Loops: Theory, Design and Applications (context) - Best - 1984
3   A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (context) - Ware - 1989
3   An 8GHz Silicon Bipolar Clock-Recovery and Data-Regenerator .. (context) - Pottbacker, Langmann
3   PLL Design for a 500MB/s Interface (context) - Horowitz
2   A Monolithic CMOS 10MHz DPLL for BurstMode Data Retiming (context) - Sonntag, Leonowitch
2   A Single-Chip, Functional Tester for VLSI Circuits (context) - Gasbarro, Horowitz
2   A 500MHz Time Digitizer IC with 15.625ps Resolution (context) - Knotts
2   A 660Mb/s Clock Recovery Circuit with Instantaneous Locking .. (context) - Banu, Dunlop - 1993
2   GHz Monolithic LC Voltage-Controlled Oscillator (context) - Nguyen, Meyer
2   A Monolithic 2.3Gb/s 100mW Clock and Data Recovery Circuit (context) - Soyuer, Ainspan
2   A 6GHz 60mW BiCMOS Phase-Locked Loop with 2V Supply (context) - Razavi, Sung
2   A 2.5V Delay-Locked Loop for an 18Mb 500MB/s DRAM (context) - Lee
2   Multifrequency Zero-Jitter Delay-Locked Loop (context) - Efendovich - 1994
2   A High-Frequency Electronically Tunable Quadrature Oscillato.. (context) - Verhoeven
1   PLL-Based BiCMOS On-Chip Clock Generator for Very HighSpeed .. (context) - Kurita - 1991
1   A 3-ns Rnage, 8-ps Resolution, Timing Generator LSI Utilizin.. (context) - Otsuji, Narumi - 1991
1   A PLL-Based 2.5-Gb/s GaAs Clock and Data Regenerator IC (context) - Ransijn, O'Connor - 1991
1   MOS Decision and Clock-Recovery Circuits for Gb/s Optical-Fi.. (context) - Enam, Abidi
1   Multigigahertz Voltage-Controlled Oscillators in Advanced Si.. (context) - Soyuer, Warnock - 1992
1   Start-up and Frequency Stability in High-Frequency Oscillato.. (context) - Nguyen, Meyer - 1992
1   Continuously Variable Gigahertz Phase-Shifter IC Covering mo.. (context) - Schmidt, Rein - 1992
1   A 1.2-um CMOS Current-Controlled Oscillator (context) - Flynn, Lidholm
1   A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/ GaAs Hete.. (context) - Buchwald - 1992
1   Phase Accuracy of Charge Pump PLL's (context) - Gardner
1   An Integrated Time Reference (context) - Blauschild
1   CMO Mbs Phase Modulation O Interface (context) - El, Mb et al.
1   A Monolithic 156Mb/s Clock and Data-Recovery PLL Circuit usi.. (context) - Ishihara, Akazawa - 1994
1   A 30-MHz Low-Jitter High-Linearity CMOS Voltage -Controlled .. (context) - Wakayama, Abidi - 1987
1   A 33Mb/s Data Synchronizing Phase-Locked-Loop Circuit (context) - Liewellyn
1   A 45-MHz CMOS Phase/Frequency-Locked Loop Timing Recovery Ci.. (context) - Leonowich, Steininger
1   100KHz - 1GHz NMOS Variable-Frequency Oscillator with (context) - Banu
1   A 250MHz Monolithic Voltage-Controlled Oscillator (context) - Liu, Meyer
1   A Low-Power 128-MHz VCO for Monolithic PLL IC's (context) - Kato - 1988
1   MOS Oscillators with Multi-Decade Tuning Range and Gigahertz.. (context) - Banu - 1988
1   An Analog PLL-Based Clock and Data Recovery Circuit with Hig.. (context) - Sun
1   High-Frequency Phase-Locked Loops in Monolithic Bipolar Tech.. (context) - Soyuer, Meyer
1   Frequency Memory in Multi-Mode Oscillators (context) - Edson - 1955
1   A 10-ps Resolution Process-Insensitive Timing Generator IC (context) - Otsuji, Narumi - 1989
1   well CMOS Process (context) - um
1   19GHz Monolithic Integrated Clock Recovery Using PLL and 0.3.. (context) - Wang
1   A 220MHz Pipelined 16Mb BiCMOS SRAM with PLL Proportional Se.. (context) - Nakamura - 1994
1   A BiCMOS Time Interval Digitizer for High-Energy Physics Ins.. (context) - Loinaz, Wooley
1   Analog Phase Measuring Circuit for Digital CMOS IC's (context) - Rothermel, Dell'ova - 1993
1   The Use of Stabilized CMOS Delay Lines for the Digitization .. (context) - Rahkonen, Kostamovaara - 1993
1   11.6-GHz 1:4 Regenerating Demultiplexer with Bit-Rotation Co.. (context) - Bagheri - 1992
1   A 300-MHz CMOS Voltage-Controlled Ring Oscillator (context) - Enam, Abidi - 1990
1   A GaAs 1.5Gb/s Clock Recovery and Data Retiming Circuit (context) - Wallace
1   A Picosecond-Accuracy, 700-MHz Range, Si-Bipolar Time Interv.. (context) - Otsuji - 1993
1   An Enhancement-Mode Voltage-Controlled Linear Resistor with .. (context) - Moon - 1990
1   A BiCMOS PLL-Based Data Separator Circuit with High Stabilit.. (context) - Miyazawa
1   A 52MHz and 155MHz Clock-Recovery PLL (context) - DeVito
1   Monolithic Mbs Clock Extraction Data Retiming (context) - Walker, Clock et al.



The graph only includes citing articles where the year of publication is known.

Documents on the same site (http://velox.stanford.edu/group/people.html):   More
Data Converters for High Speed CMOS Links - Ellersick (2001)   (Correct)
Netlist Processing For Custom Vlsi Via Pattern Matching - Chanak (1995)   (Correct)
Skew-Tolerant Circuit Design - Harris (1999)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC