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Abstract: The RAMpage memory hierarchy is an attempt at devising a comprehensive strategy to address the growing DRAM-CPU speed gap. By moving the main memory up a level to the SRAM currently used to implement the lowest-level cache, a RAMpage system in effect implements a fully associative cache with no hit penalty (in the best case). Ordinary DRAM is relegated to a paging device. This paper shows that even with an aggressive SDRAM conventional main memory (or equivalently the new Direct Rambus... (Update)
Context of citations to this paper: More
.... and DRAM becomes a paging device, to improve effectiveness of the lowest level SRAM [Machanick 1996, Machanick and Salverda 1998, Machanick et al. 1998, RAMpage 1997] Ted Lewis [1996a] discusses learning curves in more detail. 2.9 Exercises 2.1. In a car magazine, separate...
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Computer Architecture: a qualitative overview of Hennessy and.. - Machanick (2001) (Correct)
Active bibliography (related documents): More All
0.9: An SRAM Main Memory Model - Salverda (1997) (Correct)
0.8: Hardware-Software Trade-Offs in a Direct Rambus.. - Machanick, Salverda.. (1998) (Correct)
0.6: Further Cache and TLB Investigation of the RAMpage Memory.. - Machanick, Patel (2001) (Correct)
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0.9: Correction to RAMpage ASPLOS Paper - Machanick (1999) (Correct)
0.7: Preliminary Investigation of the RAMpage Memory Hierarchy - Machanick, Salverda (1998) (Correct)
0.7: Scalability of the RAMpage Memory Hierarchy - Machanick (2000) (Correct)
BibTeX entry: (Update)
P Machanick and P Salverda. Implications of Emerging DRAM Technologies for the RAMpage Memory Hierarchy, Proc. SAICSIT '98, Gordon's Bay, November 1998, pp 27--40. http://citeseer.ist.psu.edu/machanick98implications.html More
@misc{ machanick98implications,
author = "P. Machanick and P. Salverda",
title = "Implications of Emerging DRAM Technologies for the RAMpage Memory Hierarchy",
text = "P Machanick and P Salverda. Implications of Emerging DRAM Technologies
for the RAMpage Memory Hierarchy, Proc. SAICSIT '98, Gordon's Bay, November
1998, pp 27--40.",
year = "1998",
url = "citeseer.ist.psu.edu/machanick98implications.html" }
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10 Predicting and precluding problems with memory latency (context) - Boland, Dollas - 1994
6 Preliminary investigation of the rampage memory hierarchy - Machanick, Salverda - 1998
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1 The Stanford DASH multiprocessor (context) - W-D, Lam - 1996
1 The case for SRAM main memory - Machanick - 1996
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