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Abstract: The RAMpage memory hierarchy is an alternative to the traditional division between cache and main memory: main memory is moved up a level and DRAM is used as a paging device. Earlier RAMpage work has shown that the RAMpage model scales up better with the growing CPU-DRAM speed gap, especially when context switches are taken on misses. This paper investigates the effect of more aggressive first-level (L1) cache and translation lookaside buffer (TLB) implementations, with other parameters kept... (Update)
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BibTeX entry: (Update)
@misc{ machanick-further,
author = "Philip Machanick and Zunaid Patel",
title = "Further Cache and TLB Investigation of the RAMpage Memory Hierarchy",
url = "citeseer.ist.psu.edu/machanick01further.html" }
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