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Abstract: Instruction caches consume a large fraction of the total power in modern low-power microprocessors. In particular, set-associative caches, which are preferred because of lower miss rates, require greater access energy on hits than direct-mapped caches; this is because of the need to locate instructions in one of several ways. Way prediction has been proposed to reduce power dissipation in conventional set-associative caches; however, its application to CAMtagged caches, which are commonly used... (Update)
Context of citations to this paper: More
...via the program counter. Hence they are amenable to software invisible micro architectural techniques for power reduction, e.g. [16, 17, 15]. We first review the design of a low power cache. Then we explain caches tagged with content addressable memory. In section 3 we...
.... complexity; for example, way memoization is a technique which can eliminate tag checks for inter line sequential and non sequential accesses [32]. Figure 4 14 demonstrates the energy impact of the ILS optimization. For reference, the energy for doing a tag search every cycle is...
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0.4: The Span Cache: Software Controlled Tag Checks and Cache Line.. - Witchel, Asanovic (2001) (Correct)
0.4: Microprocessor Energy Characterization and Optimization through .. - Krashinsky (2001) (Correct)
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0.5: Fine-Grain CAM-Tag Cache Resizing Using Miss Tags - Zhang, Asanovic (Correct)
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4: Reducing the Frequency of Tag Compares for Low-Power I-Cache Design (context) - Panwar, Rennels - 1995
3: Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine - Lee, Barua et al. - 1998
3: Energy-efficient processor system design (context) - Burd - 2001
BibTeX entry: (Update)
Albert Ma, Michael Zhang, and Krste Asanovic. Way memoization to reduce fetch energy in instruction caches. ISCA Workshop on Complexity Effective Design, July 2001. http://citeseer.ist.psu.edu/ma01way.html More
@misc{ ma01way,
author = "A. Ma and M. Zhang and K. Asanovic",
title = "Way memoization to reduce fetch energy in instruction caches",
text = "Albert Ma, Michael Zhang, and Krste Asanovic. Way memoization to reduce
fetch energy in instruction caches. ISCA Workshop on Complexity Effective
Design, July 2001.",
year = "2001",
url = "citeseer.ist.psu.edu/ma01way.html" }
Citations (may not include all citations):136 superscalar microprocessor (context) - Yeager - 1996
132 The Alpha 21264 microprocessor (context) - Kessler - 1999
82 The Filter Cache: An energy efficient memory structure - Kin, Gupta et al. - 1997
49 CMOS RISC microprocessor (context) - Montanaro, -MHz et al. - 1996
35 Waypredicting set-associative cache for high performance and.. - Inoue, Ishihara et al. - 1999
29 Next cache line and set prediction - Calder, Grunwald - 1995
24 Architectural and compiler support for energy reduction in t.. (context) - Bellas, Hajj et al. - 1998
23 UltraSPARC-I: A four-issue processor supporting multimedia (context) - Tremblay, O'Connor - 1996
16 Reducing the frequency of tag compares for low power I-cache.. (context) - Panwar, Rennels - 1995
15 Highly-associative caches for low-power processors - Zhang, Asanovic - 2000
11 Energy-Efficient Processor System Design (context) - Burd - 2001
11 MAJC gives VLIW a new twist (context) - Gwennap - 1999
10 Energy optimization of multi-level processor cache architect.. (context) - Ko, Balsara et al. - 1995
10 Sh3: high code density (context) - Hasegawa - 1995
9 Intel XScale microarchitecture (context) - Corporation - 2001
7 quad-issue CMOS RISC microprocessor (context) - Benschneider, -MHz - 1995
5 Energy efficient cache organizations for superscalar process.. - Ghose, Kamble - 1998
4 Reducing instruction cache energy using gated wordlines (context) - Panich - 1999
4 low cost: The ARM6 family (context) - Muller - 1992
2 An integrated cache and timing model (context) - Reinman, Jouppi - 1999
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.cag.lcs.mit.edu/scale/publications.html): More
The Span Cache: Software Controlled Tag Checks and Cache Line.. - Witchel, Asanovic (2001) (Correct)
Microprocessor Energy Characterization and Optimization through .. - Krashinsky (2001) (Correct)
Exposing Datapath Elements to Reduce Microprocessor Energy.. - Hampton (2001) (Correct)
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