Patrick Lysaght, John Dunlop  Home/Search
Context Related
| drl4.eee.strath.ac.uk/p...pl_fpl93.ps.Z oak.eee.strath.ac.uk/pape...pl_fpl93.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: drl4.eee.strath.ac...publications (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: This paper considers the dynamic reconfiguration of those cellular Field Programmable Gate Arrays (FPGAs) that employ static memory to store their device configuration data. A FPGA is classified as dynamically reconfigurable if it can be partially reconfigured while active. The circuits on the device that are not included in the selective reconfiguration must continue to operate without interruption. Dynamically reconfigurable FPGAs form a new class of logic which suggests new methods of ... (Update)
Similar documents based on text: More All
0.8: Implementation of Adaptive Signal Processing Architectures.. - Lysaght, Dick (1994) (Correct)
0.7: Self Controlling Dynamic Reconfiguration: A Case Study - McGregor, Lysaght (1999) (Correct)
0.7: Dynamically Reconfigurable Cores - Macbeth, Lysaght (2001) (Correct)
BibTeX entry: (Update)
P. Lysaght and J. Dunlop, Dynamic Reconfiguration of Field Programmable Gate Arrays, in Field Programmable Logic and Applications, Oxford, England, Sept 1993 http://citeseer.ist.psu.edu/lysaght93dynamic.html More
@inproceedings{ lysaght93dynamic,
author = "P. Lysaght and J. Dunlop",
title = "Dynamic Reconfiguration of {FPGA}s",
booktitle = "More {FPGAs}: Proceedings of the 1993 International workshop on field-programmable logic and applications",
address = "Oxford, England",
editor = "W. Moore and W. Luk",
pages = "82--94",
year = "1993",
url = "citeseer.ist.psu.edu/lysaght93dynamic.html" }
Citations (may not include all citations):171 VLSI Array Processors (context) - Kung - 1988
105 The Programmable Gate Array Data Book (context) - Inc - 1991
82 Design and Analysis of Fault Tolerant Digital Systems (context) - Johnson - 1989
77 Building and Using A Highly Parallel Programmable Logic Arra.. (context) - Gokhale - 1991
52 Introduction to programmable active memories - Bertin - 1989
44 Compiling Occam into FPGAs (context) - Page, Luk - 1991
23 Third-generation architecture boosts speed and density of Fi.. (context) - Hsieh - 1990
16 A Taxonomy of reconfiguration Techniques for Fault-Tolerant .. (context) - Chean, Fortes - 1990
15 Computer Architecture A Quantitive Approach (context) - Hennessy, Patterson - 1990
11 A Stochastic Neural Architecture that exploits Dynamically R.. - Van Daalen, Jeavons et al. - 1993
7 Configurable Logic: A Dynamically Programmable Cellular Arch.. (context) - Thomas - 1989
7 The Effect of Logic Block Complexity on Area of Programmable.. (context) - Rose - 1989
3 Advanced PLD Architectures (context) - Hawley - 1991
3 Using CAL to Accelerate Maze Routing of CAL Designs (context) - Thomas - 1992
2 Dynamically Reconfigurable Logic in Undergraduate Projects (context) - Lysaght - 1991
1 Dynamically reconfigurable hardware for mixed hardware / sof.. (context) - Taylor - 1991
1 Adaptable Architectures for Supersystems (context) - Vick, Kartashev et al. - 1980
Documents on the same site (http://drl4.eee.strath.ac.uk/publications.htm): More
FAST IMPLEMENTATION OF NON LINEAR FILTERS USING FPGAs - Woolfries, Lysaght.. (1998) (Correct)
Prototyping Environment for Dynamically Reconfigurable.. - Lysaght, Dick.. (1995) (Correct)
Non Linear Image Processing on Field Programmable Gate .. - Woolfries, Lysaght.. (1998) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC