Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen  Home/Search
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Abstract: This paper proposes and evaluates software techniques that increase register file utilization for simultaneous multithreading (SMT) processors. SMT processors require large register files to hold multiple thread contexts that can issue instructions, out of order, every cycle. By supporting better inter-thread sharing and management of physical registers, an SMT processor can reduce the number of registers required and can improve performance for a given register file size. Our techniques... (Update)
Context of citations to this paper: More
.... level simulator is a detailed, stand alone, execution based simulator used extensively in previous SMT studies [22, 43, 44, 45, 46, 47, 59, 77, 81, 82, 83]. It models the processor pipeline and memory system in great detail. While the simulator excels at modelling user...
...operands are allocated. They find a 25 reduction in the number of renaming registers with little loss in performance. Lo et al. [15] investigate deallocating registers on SMT after their last use via compiler inserted annotations. They observed up to an average speedup...
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BibTeX entry: (Update)
J. Lo, S. Parekh, S. Eggers, H. Levy, and D. Tullsen. Softwaredirected register deallocation for simultaneous multithreaded processors. IEEE Transactions on Parallel and Distributed Systems, to appear. http://citeseer.ist.psu.edu/lo99softwaredirected.html More
@article{ lo99softwaredirected,
author = "J. L. Lo and S. S. Parekh and S. J. Eggers and H. M. Levy and D. M. Tullsen",
title = "Software-Directed Register Deallocation for Simultaneous Multithreaded Processors",
journal = "IEEE Transactions on Parallel and Distributed Systems",
volume = "10",
number = "9",
pages = "922--??",
year = "1999",
url = "citeseer.ist.psu.edu/lo99softwaredirected.html" }
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