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by Li-ren Liu, Hsi-chuan Chen, David H. C. Du
ftp://ftp.cs.umn.edu/dept/users/du/papers/stable.ps
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Abstract:

The estimation of signal stable ranges in a combinational circuit is very critical for determining clock time in a synchronous system. How to determine an optimal clocking period highly depends on the accuracy of the estimated shortest path length as well as the estimated longest path length in a combinational circuit. In this paper, a sensitization criterion for short paths is first proposed. Based on this sensitization criterion, an approach to calculating signal stable ranges is developed. The proposed approach allows the output stable range of a gate to be the union of the stable ranges of its input-leads in some cases. An efficient algorithm called LS-algorithm based on the proposed approach and Best-First Search is implemented. The experimental results obtained indicate the stable ranges generated by the LS-algorithm is more accurate than those produced by several previous approaches. Indexed terms: timing analysis, false path problem, path sensitization, signal stable ranges, combinational circuits.

Citations

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1 Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator – Benkoski, Strojwas - 1989
1 Optimal Clocking of Synchronous Systems – Sakallah, Mudge, et al. - 1990