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Abstract: C, these machines typically achieve only about 0.5 to 1.5 sustained IPC for real-world programs. Worse yet, most studies indicate that machine efficiency drops even lower as we extrapolate to wider machines. One recent study indicated that although a hypothetical 2-instruction-wide machine achieves IPC in the range of 0.65 to 1.40, a similar, hypothetical, 6-instruction-wide machine will achieve only 1.2 to 2.3 IPC. 1 Such data imply that the current superscalar paradigm is running into... (Update)
Context of citations to this paper: More
.... architectures which try to exploit more ILP are for example advanced superscalar processors [PPE 97] superspeculative processors [LS97] and trace processing [SV97] Intel s and HP s EPIC architecture is an example of an advanced superscalar architecture although their...
...committed or squashed) from execution. This is similar to what Lipasti and Shen employed in a microarchitecture proposed by them [16]. Our use of the issue slot is also similar to the old idea of reservation stations [26] since they are positioned in silicon in close...
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BibTeX entry: (Update)
M. H. Lipasti and J. P. Shen, "Superspeculative Microarchitecture for Beyond AD http://citeseer.ist.psu.edu/lipasti97superspeculative.html More
@article{ lipasti97superspeculative,
author = "Mikko H. Lipasti and John Paul Shen",
title = "Superspeculative Microarchitecture for Beyond {AD 2000}",
journal = "Computer",
volume = "30",
number = "9",
pages = "59--66",
year = "1997",
url = "citeseer.ist.psu.edu/lipasti97superspeculative.html" }
Citations (may not include all citations):214 Combining Branch Predictors - McFarling - 1993
190 Value Locality and Load Value Prediction - Lipasti, Wilkerson et al. - 1996
183 Trace Cache: A Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Bennett et al. - 1996
145 Exceeding the Data-Flow Limit Via Value Prediction - Lipasti, Shen - 1996
102 Dynamic Speculation and Synchronization of Data Dependences - Moshovos - 1997
97 The Case For a Single-Chip Multiprocessor (context) - Olukotun - 1996
93 Optimization of Instruction Fetch Mechanisms for High Issue .. - Conte - 1995
16 The Intrinsic Bandwidth Requirements of Ordinary Programs (context) - Huang, Shen - 1996
12 The Performance Potential of Value and Dependence Prediction - Lipasti, Shen - 1997
6 Eliminating Operand Read Latency (context) - Widigen, Sowadsky et al. - 1996
1 Electrical and Computer Eng (context) - Lipasti, Locality et al. - 1997
The graph only includes citing articles where the year of publication is known.
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Scalable Processors in the Billion-Transistor Era: IRAM - Kozyrakis, Perissakis.. (1997) (Correct)
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