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Abstract: much slower. Therefore the main memory is supported by several caches. These allow faster accesses, but due to their technology they are much smaller than main memory. (Update)
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BibTeX entry: (Update)
@misc{ lindenmaier-analysis,
author = "Götz Lindenmaier",
title = "Analysis of Profiling Information for Cache Sensitive Scheduling",
url = "citeseer.ist.psu.edu/lindenmaier99analysis.html" }
Citations (may not include all citations):474 A Data Locality Optimizing Algorithm (context) - Wolf, pp - 1991
407 Trace Scheduling: A technique for global microcode compactio.. (context) - Fisher - 1981
344 Design and evaluation of a compiler algorithm for prefetchin.. - Mowry, pp et al. - 1992
230 Limits of Instruction-Level Parallelism - Wall - 1991
173 Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1985
115 Program Optimization for instruction caches (context) - McFarling - 1989
110 Available Instruction-Level Parallelism for Superscalar and .. - Jouppi, Wall - 1989
107 Achieving High Instruction Cache Performance with an Optimiz.. (context) - Hwu, Chang - 1989
107 Global Instruction Scheduling for Super scalar Machines (context) - Bernstein, Rodeh - 1991
70 Integrating Register Allocation and Instruction Scheduling f.. (context) - Bradlee, Eggers et al. - 1991
59 Performance analysis using the MIPS R10000 performance count.. - Zagha - 1996
39 Balanced Scheduling: Instruction scheduling when memory late.. - Kerns, Eggers - 1993
33 Alias Analysis of Executable Code - Debray, Muth et al. - 1998
31 MHz 64-bit Quad-issue CMOS RISC Microprocessor (context) - Edmondson, Rubinfeld et al. - 1995
25 The Importance of Prepass Code Scheduling for Superscalar an.. - Chang, Lavery et al. - 1995
22 Cache Miss Heuristics and Preloading Techniques for General-.. (context) - Ozawa, Kimura et al. - 1995
22 Global Code Generation For Instruction-Level Parallelism: Tr.. (context) - Fisher - 1993
21 Predictability LoadStore Instruction Latencie (context) - Abraham, Daniel et al.
20 ective Scheduling Technique for VLIW Machines (context) - Lam, Pipelining - 1988
19 Quantifying Loop Nest Locality Using SPEC'95 and the Perfect.. - McKinley, Temam - 1998
16 Improving Balanced Scheduling with Compiler Optimizations th.. - Lo, Eggers - 1995
13 Optimal Code Scheduling for Delayed-Load Architectures (context) - Proebsting, Fischer - 1991
13 CRAIG: A Practical Framework for Combining Instruction Sched.. - pp, Philip et al. - 1995
11 Cache Sensitive Modulo Scheduling (context) - Sanchez, Gonzales - 1997
11 MHz 64-bit Dual-issue CMOS Microprocessor (context) - Dobberpuhl - 1992
8 IEEE Transactions on Parallel and Distributed Systems (context) - Aiken, Nicolau et al. - 1995
8 Investigating Optimal Local Memory Performance - Temam - 1998
8 Static Locality Analysis for Cache Management (context) - Sanchez, Gonzales et al. - 1997
8 Cache Miss Equations: An Analytical Representation of Cache .. (context) - Gosh, Martonisi et al. - 1997
8 Modulo Scheduling with Cache Reuse Information - Ding, Carr et al. - 1997
8 The Multi ow Trace Scheduling Compiler (context) - Geo, Lowney et al. - 1993
5 Fine-grain Parallelization and the Wavefront Method (context) - Aiken, Nicolau - 1990
4 Ecient Instruction Scheduling for a Pipelined Architecture (context) - Gibbons, pp - 1986
3 Advanced Computer Architecture (context) - Sima, Fountain et al. - 1997
3 The Organization of Microprogram Stores (context) - Dasgupta - 1979
2 Alpha Implementation and Architecture (context) - Bhandarkar - 1996
2 A New Fast Algorithm for Optimal Register Allocation in Modu.. - Lelait, Gao et al. - 1998
2 IEEE Transactions of Computers (context) - Hill, for et al. - 1988
1 The Alpha 21264: A 500 MHz Out-of-Order Microprocessor (context) - Leibholz, Razdan - 1997
1 Eziente Verfahren zur Befehlsanordnung (context) - uller - 1995
1 Practical and Pro table DAGbased Global Instruction Scheduli.. (context) - Chen, Young et al. - 1998
1 Tha Alpha AXP Architecture and 21064 Processor (context) - McLellan - 1993
1 ects of Resource Limitations on Program Parallelism (context) - Theobald, Gao et al. - 1992
1 Pro leMe: Hardware Support for Instruction Level Pro ling on.. (context) - ery, James et al. - 1997
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Documents on the same site (http://www.info.uni-karlsruhe.de/~goetz/english/index.html):
Load Scheduling with Profile Information - Lindenmaier, McKinley, Temam (2000) (Correct)
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