See this document in CiteSeerX!

An Accurate Worst Case Timing Analysis for RISC Processors (1995)  (Make Corrections)  (91 citations)
Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong Sang Kim
Software Engineering



  Home/Search   Context   Related

 
View or download:
archi.snu.ac.kr/PU...limtse1995.ps.gz
net.snu.ac.kr/arch...limtse1995.ps.gz
archi.snu.ac.kr/sslim/tse.ps
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  archi.snu.ac.kr...ealtimepapers (more)
From:  net.snu.ac.kr/a...ealtimepapers
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the... (Update)

Cited by:   More
Static Analysis Support for Measurement-based WCET Analysis - Stefan Schaefer Bernhard   (Correct)
Facilitating Worst-Case Execution Times Analysis for.. - Engblom, Ermedahl.. (1998)   (Correct)
Clustered Calculation of Worst-Case Execution Times - Ermedahl, Stappert, Engblom (2003)   (Correct)

Similar documents (at the sentence level):
40.5%:   An Accurate Worst Case Timing Analysis Technique for RISC.. - Sung-Soo Lim (1994)   (Correct)

Active bibliography (related documents):   More   All
0.8:   An Accurate Instruction Cache Analysis Technique for.. - Lim, Min, Lee, Park, .. (1994)   (Correct)
0.3:   Worst-Case Execution Time Analysis on Modern Processors - Nilsen, Rygg (1995)   (Correct)
0.3:   Supporting Control-Flow-Dependent Execution Times on WCET.. - Kirner, Puschner (2000)   (Correct)

Similar documents based on text:   More   All
0.5:   A Worst Case Timing Analysis Technique for Multiple-Issue.. - Lim, Han, al. (1998)   (Correct)
0.4:   Worst Case Timing Analysis of RISC Processors.. - Hur, Bae, Lim.. (1995)   (Correct)
0.3:   A Low-Overhead High-Performance Unified Buffer.. - Kim, Choi, Kim.. (2000)   (Correct)

Related documents from co-citation:   More   All
39:   Predicting program execution times by analyzing static and dynamic program paths (context) - Park - 1993
37:   Bounding worst-case instruction cache performance (context) - Arnold, Mueller et al. - 1994
29:   Integrating the Timing Analysis of Pipelining and Instruction Caching (context) - Healy, Whalley et al. - 1995

BibTeX entry:   (Update)

S.-S. Lim, Y. H. Bea, G. T. Jang, B.-D. Rhee, S. L. Min, Y. C. Park, H. Shin, and C. S. Kim. An accurate worst case timing analysis for RISC processors. In IEEE Real-Time Systems Symposium, pages 97--108, December 1994. http://citeseer.ist.psu.edu/lim95accurate.html   More

@article{ lim95accurate,
    author = "Sung-Soo Lim and Young Hyun Bae and Gyu Tae Jang and Byung-Do Rhee and Sang Lyul Min and Chang Yun Park and Heonshik Shin and Kunsoo Park and Soo-Mook Moon and Chong-Sang Kim",
    title = "An Accurate Worst Case Timing Analysis for {RISC} Processors",
    journal = "Software Engineering",
    volume = "21",
    number = "7",
    pages = "593-604",
    year = "1995",
    url = "citeseer.ist.psu.edu/lim95accurate.html" }
Citations (may not include all citations):
1575   Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1990
1399   Compilers Principles (context) - Aho, Sethi et al. - 1988
222   MIPS RISC Architecture (context) - Kane, Heimrich - 1991
167   Calculating the MaximumExecution Time of Real-Time Programs (context) - Puschner, Koza - 1989
103   Experiments with a Program Timing Tool Based on Source-Level.. (context) - Park, Shaw - 1990
102   A Characterization of the Minimum Cycle Mean in a Digraph (context) - Karp - 1978
97   The Architecture of Pipelined Computers (context) - Kogge - 1981
93   Aspects of Cache Memory and Instruction Buffer Performance (context) - Hill - 1987
92   Reasoning About Time in Higher-Level Language Software - Shaw - 1989
85   Predicting Program Execution Times by Analyzing Static and D.. (context) - Park - 1993
83   A Retargetable Technique for Predicting Execution Time - Harmon, Baker et al. - 1992
83   Bounding Worst-Case Instruction Cache Performance (context) - Arnold, Mueller et al. - 1994
69   Register Allocation by Priority-based Coloring (context) - Chow, Hennessy - 1984
63   A Code Generation Interface for ANSI C - Fraser, Hanson - 1990
55   Pipelined Processors and Worst-Case Execution Times - Zhang, Burns et al. - 1993
54   Evaluating Tight Execution Time Bounds of Programs by Annota.. (context) - Mok - 1989
37   Look-ahead Processors (context) - Keller - 1975
35   Software-Based Cache Partitioning for Real-time Applications (context) - Wolfe - 1993
28   Cummings Publishing Company (context) - Fischer, LeBlanc et al. - 1991
23   SMART (Strategic Memory Allocation for Real-Time) Cache Desi.. (context) - Kirk - 1989
21   A Real-Time Language with a Schedulability Analyzer (context) - Stoyenko - 1987
20   Predicting Deterministic Execution Times of Real-Time Progra.. (context) - Park - 1992
18   Static Analysis of Cache Performance for Real-Time Programmi.. (context) - Rawat - 1993
17   Predictable Real-Time Caching in the Spring System (context) - Niehaus, Nahum et al. - 1991
13   Portable Execution Time Analysis for RISC Processors (context) - Narasimhan, Nilsen - 1994
13   Deterministic Upperbounds of the Worst-Case Execution Times .. (context) - Liu, Lee - 1994
3   Data Cache Analysis Techniques for Real-Time Systems (context) - Bae - 1995
3   Timing Analysis of Superscalar Processor Programs Using ACSR - Choi, Lee et al. - 1994
3   Instruction Cache and Pipelining Analysis Technique for Real.. (context) - Lim - 1995
2   High-Level Timing Specification of Instruction-Level Paralle.. - Harcourt, Mauney et al. - 1993
1   Retargetable Timing Analyzer for RISC Processors - Rhee, Min et al. - 1994



The graph only includes citing articles where the year of publication is known.


Documents on the same site (http://archi.snu.ac.kr/PUBLICATIONS/real-time-papers.html):   More
An Accurate Instruction Cache Analysis Technique for.. - Lim, Min, Lee, Park, .. (1994)   (Correct)
Enhanced Analysis of Cache-related Preemption Delay.. - Lee, Hahn, Seo.. (1997)   (Correct)
Worst Case Timing Analysis of RISC Processors.. - Hur, Bae, Lim.. (1995)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC