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Abstract: Dynamic memory management usually stresses the randomness of data memory usage; the variables of a dynamic cache working set are to some degree distributed stochastically in the virtual or physical address space. This interferes with cache and TLB architectures, since, currently, most of them are highly sensitive to access patterns. In the above mentioned stochastically distributed case, the true capacity is (a) far below the cache or TLB size and (b) largely differs from processor to... (Update)
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BibTeX entry: (Update)
@techreport{ liedtke95potential,
author = {Liedtke, J.},
title = {Potential Interdependencies Between Caches, {TLB}s and Memory Management Schemes},
institution = {GMD --- German National Research Center for Information Technology},
year = 1995,
type = {Arbeitspapiere der GMD No.},
number = 962,
address = {Sankt Augustin},
month = dec,
url = {citeseer.ist.psu.edu/liedtke95potential.html} }
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