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Abstract: Address-space switch requires a TLB flush on many processors. With increasing TLB size, the secondary costs of address-space switching due to TLB refill can thus increase substantially. For the Pentium processor, we describe an optimization to avoid TLB flush in many cases. The method is transparent to the user and thus requires no extension of the micro-kernel interface. (Update)
Context of citations to this paper: More
...of the driving forces behind the current resurgence of interest in microkernel based systems. In particular, IPC implementations by Liedtke [20, 21], and Shapiro [30] have shown that protected IPC invocations can be reduced into the 135 cycle range on Pentiumfamily processors....
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BibTeX entry: (Update)
Liedtke, J. 1995. Improved address-space switching on Pentium processors by transparently multiplexing user address spaces. Arbeitspapiere der GMD No. 933 (Sept.), GMD --- German National Research Center for Information Technology, Sankt Augustin. http://citeseer.ist.psu.edu/liedtke95improved.html More
@techreport{ liedtke95improved,
author = {Jochen Liedtke},
title = {Improved Address-Space Switching on {P}entium Processors by Transparently Multiplexing User Address Spaces},
type = {Arbeitspapiere der GMD No.},
institution={GMD --- German National Research Center for Information Technology},
address = {Sankt Augustin},
number = 933,
month = sep,
year = 1995,
url = {citeseer.ist.psu.edu/liedtke95improved.html} }
Citations (may not include all citations):222 MIPS Risc Architecture (context) - Kane, Heinrich - 1992 ACM
98 Improving IPC by kernel design - Liedtke - 1993 ACM DBLP
18 Pentium Processor User's Manual (context) - Corp - 1993
7 PowerPC 601 RISC Microprocessor User's Manual (context) - Inc - 1993
5 i486 Microprocessor Programmer's Reference Manual (context) - Corp - 1990 ACM
3 DECChip 21064-AA Risc Microprocessor Data Sheet (context) - Corp - 1992
The graph only includes citing articles where the year of publication is known.
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