Abstract:
We address the problem of verification of implementations of complex processors using architectural level automatic test program generators. A number of automatic test program generators exist, and are widely used for verification of the compliance of complex processors with their architectures. We define a four stage verification process: (1) describing the processor implementation control as a Finite State Machine (2) deriving transition coverage on the FSM using methods from formal verification (3) translation of the covering tours to constraints on test programs (4) generation of test programs for each set of constraints. This process combines a high quality and well defined theoretical method along with tools used in industrial practice. There are a number of advantages of our Method: (a) The last three stages are automated (b) Implementing the FSM model involves relatively little expert designers time (c) The method is feasible for modern superscalar processors and was studied on an enhanced PowerPC processor. We describe a formal framework for the new process, identify the obstacles that are encountered in the modeling phase, and show how to overcome them.
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