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Abstract: We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital signal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was implemented to reduce the average number of required iterations. This leads to an implementation with increased throughput compared to other implementations of LDPC codes or Turbo codes. This decoder is able to decode at 5.4Mbps on a ... (Update)
Active bibliography (related documents): More All
0.0: Near Shannon Limit Performance of Low Density Parity Check Codes - MacKay, Neal (1996) (Correct)
0.0: Linear Systems Analysis And Decoding Of Convolutional Codes - Allen (1999) (Correct)
0.0: Which Codes Have Cycle-Free Tanner Graphs? - Etzion, Trachtenberg, Vardy (1998) (Correct)
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BibTeX entry: (Update)
@misc{ lechner-efficient,
author = "Gottfried Lechner and Jossy Sayir and Markus Rupp",
title = "Efficient DSP Implementation of an LDPC Decoder",
url = "citeseer.ist.psu.edu/lechner04efficient.html" }
Citations (may not include all citations):559 Near Shannon limit error-correcting coding and (context) - Berrou, Glavieux et al.
341 Low density parity check codes (context) - Gallager - 1962
Documents on the same site (http://www.gottfriedlechner.com): More
Analyzing the Effect of Redundant Parity-Checks Using.. - Lechner, Wohlgenannt.. (2003) (Correct)
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On the Convergence of Log-Likelihood Values in Iterative Decoding - Lechner, Sayir (Correct)
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