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Abstract: This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configurable caches) and regular accesses (via pre-fetching stream buffers). By hiding specifics behind a consistent abstract interface, it is suitable as a target environment for automatic hardware compilation. (Update)
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BibTeX entry: (Update)
H. Lange and A. Koch. Memory access schemes for configurable processors. In Proceedings of the 10th International on Field-Programmable Logic and Applications, pages 615--25, Villach, Austria, Aug. 2000. http://citeseer.ist.psu.edu/lange00memory.html More
@inproceedings{ lange00memory,
author = "Holger Lange and Andreas Koch",
title = "Memory Access Schemes for Configurable Processors",
booktitle = "{FPL}",
pages = "615-625",
year = "2000",
url = "citeseer.ist.psu.edu/lange00memory.html" }
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1 NAPA C: Compiling for a Hybrid RISC/FPGA Machine (context) - Gokhale, Stone - 1998
1 A Comprehensive Platform for Hardware-Software Co-Design (context) - Koch - 2000
1 Configurable Cache (context) - Fung, Pan - 1998
1 Dynamically programmable cache (context) - Harding, Schwartz - 1998
1 Maximizing Bandwidth for Streamed Computations (context) - McKee - 1995
1 A Hardware/Software Codesign Method for a General-Purpose Re.. (context) - Kimura, Yukishita et al. - 1997
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