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Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures (2001)  (Make Corrections)  (7 citations)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey



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Abstract: The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system architecture for a specific application or domain, makes it critical for a designer to be aware of (and to evaluate) the trade-offs involved in selecting an optimal system-level communication architecture. While it is generally known that different communication architectures may be better suited to serve the needs of... (Update)

Context of citations to this paper:   More

.... their pros and cons, none of them uniformly outperform otherstheir performance highly depends on the specific application domains [6][7] 8] In this paper, we focus primarily on the performance analysis of shared bus communication architecture for sacs, especially the case...

.... communication architectures too display a wide variance in their utilization, depending on the communication patterns of applications [31]. The DVS algorithm presented in [29] is a variant of previously proposed history based DVS techniques for processors, and adapts the...

Cited by:   More
Rate Analysis for Streaming Applications with On-chip.. - Maxiaguine, Künzli, al. (2004)   (Correct)
A Survey of Techniques for Energy Efficient On-Chip.. - Raghunathan.. (2003)   (Correct)
On the Performance of Bus Interconnection for SOCs - Zhang, Chaudhary   (Correct)

Active bibliography (related documents):   More   All
0.5:   Efficient Exploration of the SoC Communication.. - Lahiri, Raghunathan, Dey (2000)   (Correct)
0.5:   LOTTERYBUS: A New High-Performance Communication.. - Lahiri.. (2001)   (Correct)
0.5:   Networks on Silicon: Blessing or Nightmare? - Paul Wielage And (2002)   (Correct)

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0.9:   Communication Architecture Based Power Management for.. - Lahiri, Raghunathan, Dey (2002)   (Correct)
0.8:   Fast System-Level Power Profiling for Battery-Efficient.. - Lahiri, Raghunathan, Dey (2002)   (Correct)
0.6:   High-level Synthesis of Multi-process Behavioral.. - Wang, Raghunathan, Jha, Dey   (Correct)

Related documents from co-citation:   More   All
4:   not wires: On-chip interconnection networks (context) - Dally, Towles - 2001
4:   Traffic analysis for on-chip networks design of multimedia applications (context) - Varatkar - 2002
3:   A framework for evaluating design tradeoffs in packet processing architectures - Thiele, Chakraborty et al. - 2002

BibTeX entry:   (Update)

K. Lahiri, A. Raghunathan, and S. Dey, "Evaluation of the traffic performance characteristics of system-on-chip communication architectures," in Proc. Int. Conf. VLSI Design, pp. 29--35, Jan. 2001. http://citeseer.ist.psu.edu/lahiri01evaluation.html   More

@misc{ lahiri01evaluation,
  author = "K. Lahiri and A. Raghunathan and S. Dey",
  title = "Evaluation of the traffic performance characteristics of system-on-chip
    communication architectures",
  text = "K. Lahiri, A. Raghunathan, and S. Dey, Evaluation of the traffic performance
    characteristics of system-on-chip communication architectures, in Proc.
    Int. Conf. VLSI Design, pp. 29--35, Jan. 2001.",
  year = "2001",
  url = "citeseer.ist.psu.edu/lahiri01evaluation.html" }
Citations (may not include all citations):
624   Computer Networks (context) - Tanenbaum - 1989
277   Ptolemy: A framework for simulating and prototyping heteroge.. - Buck - 1994
161   Hardware-software Co-Design of Embedded Systems: The POLIS A.. (context) - Balarin - 1997
73   Interface Based Design (context) - Rowson, Sangiovanni-Vincentelli - 1997
45   Communication synthesis for distributed embedded systems (context) - Yen, Wolf - 1995
30   Bus-based communication synthesis on system level (context) - Gasteier, Glesner - 1999
26   Integrating communication protocol selection with partitioni.. - Knudsen, Madsen - 1998
21   Architectural choices in large scale ATM switches - Turner, Yamanaka - 1998
19   Synthesis of systemlevel communication by an allocation base.. (context) - Daveau, Ismail et al. - 1995
15   Optimizing Communication in embedded system cosimulation - Hines, Borriello - 1997
10   Performance analysis of systems with multi-channel communica.. - Lahiri, Raghunathan et al. - 2000
9   Fast performance analysis of bus-based system-on-chip commun.. - Lahiri, Raghunathan et al. - 1999
8   Performance analysis of a system of communication processes (context) - Dey, Bommu - 1997
2   On chip bus attributes specification 1 OCB (context) - attributes, On et al.
2   Open Core Protocol Specification version (context) - Protocol, http et al. - 1999



The graph only includes citing articles where the year of publication is known.


Documents on the same site (http://www.ee.princeton.edu/~anand/publications.html):   More
Performance Analysis of Systems With Multi-Channel.. - Lahiri, Raghunathan, Dey (2000)   (Correct)
Power Analysis of Embedded Operating Systems - Dick, Lakshminarayana.. (2000)   (Correct)
Design for Testability Techniques At the Behavioral and.. - Dey, Raghunathan, Wagner (1998)   (Correct)

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