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Abstract: Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven knowledge of procedure invocation patterns. On a multithreaded architecture, however, more conflicts may arise between threads than between procedures on the same thread. This research examines opportunities for the compiler to optimize instruction cache layout on a multithreaded architecture. We examine scenarios where ... (Update)
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BibTeX entry: (Update)
@misc{ kumar-compiling,
author = "Rakesh Kumar and Dean M. Tullsen",
title = "Compiling for Instruction Cache Performance on a Multithreaded Architecture",
url = "citeseer.ist.psu.edu/kumar02compiling.html" }
Citations (may not include all citations):251 Simultaneous multithreading: Maximizing on-chip parallelism - Tullsen, Eggers et al. - 1995
186 Exploiting choice: Instruction fetch and issue on an impleme.. - Tullsen, Eggers et al. - 1996
183 Profile guided code positioning (context) - Pettis, Hansen - 1990
115 Program optimization for instruction caches (context) - McFarling - 1989
107 Achieving high instruction cache performance with an optimiz.. (context) - Hwu, Chang - 1989
80 Avoiding conflict misses dynamically in large direct-mapped .. - Bershad, Lee et al. - 1994
53 Procedure placement using temporal ordering information - Gloy, Blackwell et al. - 1997
51 Optimizing instruction cache performance for operating syste.. - Torrellas, Xia et al. - 1995
47 Efficient procedure mapping using cache line coloring - Hashemi, Kaeli et al. - 1997
40 Sparcle: An evolutionary processor design for large-scale mu.. - Agarwal, Kubiatowicz et al. - 1993
38 Compiler-directed page coloring for multiprocessors (context) - Bugnion, Anderson et al. - 1996
35 Simulation and modeling of a simultaneous multithreading pro.. (context) - Tullsen - 1996
25 Symbiotic jobscheduling for a simultaneous multithreading ar.. - Snavely, Tullsen - 2000
15 Handling long-latency loads in a simultaneous multithreading.. - Tullsen, Brown - 2001
12 Improving instruction locality with just-in-time code layout - Chen, Leupen - 1997
10 Reducing cache misses using hardware and software page place.. - Sherwood, Calder et al. - 1999
8 Microprocessor Report (context) - multithreading - 2001
4 Temporal-based procedure reordering for improved instruction.. (context) - Kalamantianos, Kaeli - 1998
4 Atom:a system for building customised program analysis tools (context) - Srivastava, Eustace - 1994
4 Impulsebuilding smart memory controller (context) - Stoller, Brunvand et al. - 1999
2 Data relocation and prefetching for large data sets (context) - Yamada, Gyllenhaal et al. - 1994
1 Microprocessor Report (context) - SMT, alpha - 1999
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