Venkata Krishnan, Josep Torrellas  Home/Search
Context Related
| uiuc.edu/iacomapaper...extendpact99.ps uiuc.edu/multithreading/iac...pact99.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: uiuc.edu/papers (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Chip-multiprocessor (CMP) architectures are a promising design alternative to exploit the everincreasing number of transistors that can be put on a die. To deliver high performance on applications that cannot be easily parallelized, CMPs can use additional support for speculatively executing the possibly data-dependent threads of an application. For cross-thread dependences that must be handled dynamically, the threads can be made to synchronize and communicate either at the register level ... (Update)
Context of citations to this paper: More
...and use of pointers and runtime inputs. One promising alternative for overcoming this problem is Thread Level Speculation (TLS) [2, 7, 14, 15, 16, 20, 23, 26, 32, 35] which allows the compiler to create parallel threads without having to prove that they are independent. a)...
...due to their use of pointers, complex data and control structures, and run time inputs. Thread Level Speculation (TLS) [1, 7, 13, 14, 15, 19, 20, 25, 30, 34] is a potential solution to this problem since it allows the compiler to create parallel threads without having to prove...
Cited by: More
Compiler Optimization of Value Communication for Thread-Level.. - Zhai (2005) (Correct)
Hardware Support for Thread-Level Speculation - Steffan (2003) (Correct)
Compiler Optimization of Scalar Value Communication.. - Zhai, Colohan.. (2002) (Correct)
Similar documents (at the sentence level):
21.7%: Speculative Multithreading Architectures - Krishnan (1998) (Correct)
15.6%: A Chip-Multiprocessor Architecture with Speculative.. - Krishnan, Torrellas (1999) (Correct)
Active bibliography (related documents): More All
0.2: A Technology-Scalable Architecture For Fast Clocks.. - Sankaralingam.. (2001) (Correct)
0.2: A Technology-Scalable Architecture for Fast Clocks.. - Sankaralingam.. (2001) (Correct)
0.2: Scheduling for ReMove and other partially connected architectures - Roos (2001) (Correct)
Similar documents based on text: More All
0.3: Eliminating Squashes Through Learning Cross-Thread.. - Cintra, Torrellas (2002) (Correct)
0.3: Exploring the Design Space of Future CMPs - Huh, Burger, Keckler (2001) (Correct)
0.2: Speculative Synchronization: Applying Thread-Level.. - Martinez, Torrellas (2002) (Correct)
Related documents from co-citation: More All
7: Techniques for Speculative Run-Time Parallelization of Loops - Gupta, Nim - 1998
7: Speculative Versioning Cache - Gopal, Vijaykumar et al. - 1998
6: A Dynamic Multithreading Processor - Akkary, Driscoll
BibTeX entry: (Update)
V. Krishnan and J. Torrellas. The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. In International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999. http://citeseer.ist.psu.edu/krishnan99need.html More
@article{ krishnan01need,
author = "Venkata Krishnan and Josep Torrellas",
title = "The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors",
journal = "International Journal of Parallel Programming",
volume = "29",
number = "1",
pages = "3--33",
year = "2001",
url = "citeseer.ist.psu.edu/krishnan99need.html" }
Citations (may not include all citations):320 MediaBench: A Tool for Evaluating and Synthesizing Multimedi.. - Lee, Potkonjak et al. - 1997
269 Multiscalar Processors - Sohi, Breach et al. - 1995
197 Maximizing Multiprocessor Performance with the SUIF Compiler - Hall, Anderson et al. - 1996
183 Trace Cache: A Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Bennett et al. - 1996
157 Architecture and applications of the HEP multiprocessor comp.. (context) - Smith - 1984
136 Parallel Programming with Polaris (context) - Blume, Doallo et al. - 1996
125 Trace Processors - Rotenberg, Jacobson et al. - 1997
76 Will Physical Scalability Sabotage Performance Gains - Matzke - 1997
74 Speculative Versioning Cache - Gopal, Vijaykumar et al. - 1998
72 Data Speculation Support for a Chip Multiprocessor (context) - Hammond, Willey et al. - 1998
70 The Superthreaded Architecture: Thread Pipelining with Run-T.. - Tsai, Yew - 1996
56 Machine Multicomputer (context) - Fillo, Keckler et al. - 1995
53 Improving Superscalar Instruction Dispatch and Issue by Expl.. - Vajapeyam, Mitra - 1997
36 Architecture: Compiler-Assisted Fine-Grained Multithreading (context) - Dubey, O'Brien et al. - 1995
30 Clustered Speculative Multithreaded Processors - Marcuello, Gonzalez - 1999
30 A Chip-Multiprocessor Architecture with Speculative Multithr.. - Krishnan, Torrellas - 1999
28 The Anatomy of the Register File in a Multiscalar Processor - Breach, Vijaykumar et al. - 1994
23 ARB: A Hardware Mechanism for Dynamic Memory Disambiguation (context) - Franklin, Sohi - 1996
21 Task Selection for a Multiscalar Processor - Vijaykumar, Sohi - 1998
20 Converting Thread-Level Parallelism Into InstructionLevel Pa.. (context) - Lo, Eggers et al. - 1997
17 MINT: A Front End for Ecient Simulation of Shared-Memory Mul.. (context) - Veenstra, Fowler - 1994
17 A Direct-Execution Framework for Fast and Accurate Simulatio.. - Krishnan, Torrellas - 1998
16 PA-8500: The Continuing Evolution of the PA-8000 Family (context) - Lesartre, Hunt - 1997
13 The Potential for Using Thread-Level Data Speculation to Fac.. (context) - Ste, Mowry - 1998
12 Microprocessor Chipset (context) - Technologies - 1994
4 Register Trac Analysis for Streamlining Inter-Operation Comm.. (context) - Franklin, Sohi - 1992
2 The Perfect Club Benchmarks (context) - Berry - 1989
1 SMA: A Speculative Multithreaded Architecture (context) - Xiao, Zhou et al. - 2000
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://iacoma.cs.uiuc.edu/papers.html): More
Comprehensive Hardware and Software Support for Operating.. - Xia, Torrellas (1999) (Correct)
Software Trace Cache - Ramírez, Larriba-Pey.. (1999) (Correct)
An Efficient Algorithm for the Run-time Parallelization of .. - Chen, Torrellas, Yew (1994) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC