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A Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors (1998)  (Make Corrections)  (17 citations)
Venkata Krishnan, Josep Torrellas
IEEE PACT



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Abstract: Multiprocessor system evaluation has traditionally been based on direct-execution based Execution-Driven Simulations (EDS). In such environments, the processor component of the system is not fully modeled. With wideissue superscalar processors being the norm in today's multiprocessor nodes, there is an urgent need for modeling the processor accurately. However, using directexecution to model a superscalar processor has been considered an open problem. Hence, current approaches model the... (Update)

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...hardware being modeled. Krishnan and Torrellas examined experimental errors in multiprocessor simulations due to simple processor models [18]. Cain et al. 5] discussed issues related to simulation precision and accuracy. In our infrastructure, we use TFsim to increase the...

...bit wide) with two 2K entry PHTs. Table 1 shows some parameters of the simulated system. We use a MINT based execution driven simulator [9] that models the contention and occupancy of all resources as the evaluation tool. The simulator incorporates Wattch [4] to evaluate...

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BibTeX entry:   (Update)

V. Krishnan and J. Torrellas. A Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors. In Proc. Parallel Architectures and Compilation Techniques, October 1998. http://citeseer.ist.psu.edu/krishnan98directexecution.html   More

@inproceedings{ krishnan98directexecution,
    author = "Venkata Krishnan and Josep Torrellas",
    title = "An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors",
    booktitle = "{IEEE} {PACT}",
    pages = "286-293",
    year = "1998",
    url = "citeseer.ist.psu.edu/krishnan98directexecution.html" }
Citations (may not include all citations):
386   ATOM: A System for Building Customized Program Analysis Tool.. (context) - Srivastava, Eustace - 1994
357   The Directory-based Cache Coherence Protocol for the DASH Mu.. (context) - Lenoski, Laudon et al. - 1990
353   The SPLASH-2 Programs: Characterization and Methodological C.. - Woo, Ohara et al. - 1995  DBLP
353   Software Pipelining: An Effective Scheduling Technique for V.. (context) - Lam - 1988
320   MediaBench: A Tool for Evaluating and Synthesizing Multimedi.. - Lee, Potkonjak et al. - 1997
275   Shade: A Fast Instruction-Set Simulator for Execution Profil.. - Cmelik, Keppel - 1994  ACM   DBLP
230   Limits of Instruction Level Parallelism - Wall - 1991
186   Exploiting Choice: Instruction Fetch and Issue on an Impleme.. - Tullsen, Eggers et al. - 1996
160   IMPACT: An Architectural Framework for MultipleInstruction -.. - Chang, Mahlke et al. - 1991
156   The Multiflow Trace Scheduling Compiler - Lowney, Freudenberger et al. - 1993  ACM
150   PROTEUS: A High-Performance Parallel-Architecture Simulator - Brewer, Dellarocas et al. - 1991  ACM   DBLP
147   Alternative Implementations of TwoLevel Adaptive Branch Pred.. - Yeh, Patt - 1992
142   MINT: A Front End for Efficient Simulation of Shared-Memory .. - Veenstra, Fowler - 1994  DBLP
110   Improving the Accuracy of Dynamic Branch Prediction Using Br.. (context) - Pan, So et al. - 1992  ACM   DBLP
109   Advanced Compiler Design Implementation (context) - Muchnick - 1997
109   Multiprocessor Simulation and Tracing using Tango (context) - Davis, Goldschmidt et al. - 1991
87   Complete Computer System Simulation: The SimOS Approach - Rosenblum, Herrod et al. - 1995
70   Design Tradeoff for Software-Managed TLBs - Uhlig, Nagle et al. - 1995
49   The Impact of Instruction-Level Parallelism on Multiprocesso.. - Pai, Ranganathan et al. - 1997
43   A Single-Chip Multiprocessor - Hammond, Nayfeh et al. - 1997  ACM   DBLP
36   Characterizing the Caching and Synchronization Performance o.. (context) - Torrellas, Gupta et al. - 1992  ACM   DBLP
35   A Comparison of Trace-Sampling Techniques for Multi-Megabyte.. - Kessler, Hill et al. - 1994  ACM   DBLP
33   Wisconsin Wind Tunnel II: A Fast and Portable Parallel Archi.. - Mukherjee, Reinhardt et al. - 1997
32   RSIM: An Execution-Driven Simulator for ILP-Based Shared-Mem.. - Pai, Ranganathan et al. - 1997
31   A Model for Estimating Trace-Sample Miss Ratios - Wood, Hill et al. - 1991
31   Execution-Driven Tools for Parallel Simulation of Parallel A.. - Poulsen, Yew - 1993
29   The Augmint Multiprocessor Simulation Toolkit for Intel x86 .. - Nguyen, Michael et al. - 1996  ACM   DBLP
15   A Critique of Trace-Driven Simulation for SharedMemory Multi.. (context) - Bitar - 1990
13   Execution-Driven Simulation of Multiprocessors: Address and .. - Dwarkadas, Jump et al. - 1994  DBLP
12   Microprocessor Chipset (context) - Technologies - 1994
11   Center for Integrated Systems (context) - Smith, Pixie et al. - 1991
10   The Design of the Microarchitecture of UltraSPARC (context) - Tremblay, Greenley et al. - 1995
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The graph only includes citing articles where the year of publication is known.


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Efficient Use of Processing Transistors for Larger On-Chip.. - Krishnan, Torrellas (1997)   (Correct)
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