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Abstract: This paper discusses the potential use of Processing-InMemory (PIM) Technology in petaflops level computing. It starts with a quick review of a proposed PIM architecture called Shamrock, and follows that up with a discussion of several execution models that the architecture supports. Sizings for a petaflops-level machine constructed solely from PIM devices at several points in time are given. This is then projected to how PIM architectures will play a pivotal role in the recently initiated HTMT ... (Update)
Context of citations to this paper: More
.... the next generation of memory chips will combine processors and memory on the same chip, this is called processing in memory (PIM) [9, 7]. Such memory components can assist the processor in accomplishing a task. Consequently, memory assisted computations will become...
.... SPELLs [7] a network based on RSFQ (Rapid Single Flux Quantum) logic devices (called CNET [19] Processor In Memory (PIM) technology [13], a high performance optical packet switched network (called Data Vortex [5] optical holographic storage devices (called HRAM [16] and...
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BibTeX entry: (Update)
Peter M. Kogge, Jay B. Brockman, Thomas Sterling, and Guang Gao. Processing in memory: Chips to petaflops. In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97. http://iram.cs.berkeley.edu/isca97-workshop/, Denver, CO, June 1997. http://citeseer.ist.psu.edu/kogge97processing.html More
@misc{ kogge97processing,
author = "P. Kogge and J. Brockman and T. Sterling and G. Gao",
title = "Processing in memory: Chips to petaflops",
text = "Peter M. Kogge, Jay B. Brockman, Thomas Sterling, and Guang Gao. Processing
in memory: Chips to petaflops. In Workshop on Mixing Logic and DRAM: Chips
that Compute and Remember at ISCA '97. http://iram.cs.berkeley.edu/isca97-workshop/,
Denver, CO, June 1997.",
year = "1997",
url = "citeseer.ist.psu.edu/kogge97processing.html" }
Citations (may not include all citations):97 The Architecture of Pipelined Computers (context) - Kogge - 1981
92 The Message Driven Processor: A Multicomputer Processing Nod.. - Dally - 1992
45 A Case for Intelligent RAM - Patterson - 1997
38 Building Multithreaded Architectures with Off-theShelf Micro.. - Hum, Theobald et al. - 1994
19 Enabling Technologies for Petaflops Computing (context) - Sterling, Messina - 1995
18 Combined DRAM and Logic Chip for Massively Parallel Applicat.. (context) - Kogge, Sunaga et al. - 1995
18 The EXECUBE Approach to Massively Parallel Processing (context) - Kogge
17 Hybrid Technology Multithreaded Architecture (context) - Gao, Likharev et al. - 1996
10 The Architecture of Symbolic Computers (context) - Kogge - 1991
7 A Novel High-Speed Memory Organization for Fine-Grain Multi-.. (context) - Hum, Gao - 1991
7 Pursuing a Petaflop: Point designs for 100TF Computers Using.. (context) - Kogge, Bass et al. - 1996
5 Bounds on Memory Bandwidth in Streamed Computations - McKee, Wulf et al. - 1995
3 A Parallel Processing Chip with Embedded DRAM Macros (context) - Sunaga, Kogge - 1996
2 Final Report: Scalable Spaceborne Computing Using PIM Techno.. (context) - Szczerba - 1996
1 Petaflops, Algorithms, and PIMs (context) - Kogge, Brockman et al.
1 Based Architectures for Petaflops Potential Massively Parall.. (context) - Kogge - 1996
1 Steps to Petaflops Computing: A Hybrid Technology Multithrea.. (context) - Sterling, Gao et al. - 1997
1 The Case for PIM (context) - Brockman, Kogge - 1997
The graph only includes citing articles where the year of publication is known.
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