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Abstract: Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an execution model to overcome mis-speculation penalties by executing both paths after diffident branches. We present the micro-architecture of the PolyPath processor, which is an extension of an aggressive superscalar, out-of-order architecture. The PolyPath architecture uses a novel instruction tagging and register... (Update)
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0.5: Realizing High IPC Using Time-Tagged Resource-Flow.. - Uht, Khalafi, Morano.. (2002) (Correct)
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BibTeX entry: (Update)
A. Klauser, A. Paithankar, and D. Grunwald. Selective Eager Execution on the PolyPath Architecture. In 25th Intl. Symp. on Computer Architecture, Barcelona, Spain, June 1998. http://citeseer.ist.psu.edu/klauser98selective.html More
@inproceedings{ klauser98selective,
author = "Artur Klauser and Abhijit Paithankar and Dirk Grunwald",
title = "Selective Eager Execution on the PolyPath Architecture",
booktitle = "{ISCA}",
pages = "250-259",
year = "1998",
url = "citeseer.ist.psu.edu/klauser98selective.html" }
Citations (may not include all citations):214 Combining Branch Predictors - McFarling - 1993
82 Assigning Confidence to Conditional Branch Predictions - Jacobsen, Rotenberg et al. - 1996
81 Implementing Precise Interrupts in Pipelined Processors (context) - Smith, Pleszkun - 1988
57 The Agree Predictor: A Mechanism for Reducing Negative Branc.. - Sprangle, Chappell et al. - 1997
47 Disjoint Eager Execution: An Optimal Form of Speculative Exe.. - Uht, Sindagi et al. - 1995
46 Confidence Estimation for Speculation Control - Grunwald, Klauser et al. - 1998
43 Control Flow Speculation in Multiscalar Processors - Jacobson, Bennett et al. - 1997
40 Multiple-Block Ahead Branch Predictors - Seznec, Jourdan et al. - 1996
31 MHz 64-bit Quad-issue CMOS RISC Microprocessor (context) - Edmondson, of et al. - 1995
31 Value Locality and Speculative Execution - Lipasti - 1997
28 A Comparison of Dynamic Branch Predictors that use Two Level.. (context) - Yeh, Patt - 1993
26 Selective Dual Path Execution - Heil, Smith - 1996
19 Limited Dual Path Execution (context) - Lick - 1996
19 Limited Dual Path Execution (context) - Tyson, Lick et al. - 1997
16 AINT: A Tool for Simulation of SharedMemory Multiprocessors (context) - Paithankar - 1996
13 A Three Dimensional Register File for Superscalar Processors (context) - Tremblay, Joy et al. - 1995
11 Superscalar Microprocessor (context) - Yeager - 1996
10 and Jim Smith (context) - Rotenberg, Jacobson et al. - 1997
6 Pipe: A Conditional Branching Scheme Without Pipeline Delays (context) - Knieser, Papachristou - 1992
6 The BiMode Branch Predictor (context) - Lee, Chen et al. - 1997
3 Integrating a Misprediction Recovery Cache into a Superscala.. (context) - Bondi, Nanda et al. - 1996
2 Supporting Highly Speculative Execution via Adaptive Branch .. - Chen - 1998
2 Alpha AXP-21164 Processor Hardware Reference Manual (context) - Semiconductor - 1997
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