See this document in CiteSeerX!

Precharging Cache : A Context-Switch Robust Cache Organization (1994)  (Make Corrections)  
Jong Min Kim



  Home/Search   Context   Related

 
View or download:
archi.snu.ac.kr/jmkim...prechargnew.ps
Cached:  PDF   PS.gz  PS  Image  Update  Help

From:  realtime.snu.ac.kr/jmkim/ (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: In current high-performance processors with cache memories, the relative cost of a cache miss in terms of processor cycles has become too high. The cache misses resulting from context switches take an increasingly large portion of the total cache misses as the size and set-associativity of the cache memory increases. In this paper, we propose and analyze a novel cache organization, called precharging cache, that aims at reducing the number of cache misses resulting from context switches. The... (Update)

Active bibliography (related documents):   More   All
0.5:   Implementation and Performance Evaluation of the LRFU .. - Lee, Choi, Choe.. (1997)   (Correct)
0.4:   Accepted for publication in Microprocessors and Microsystems. - Te Ms (1998)   (Correct)
0.3:   Knowledge Of Characteristics In Multiprogrammed Multiprocessor.. - Parsons (1997)   (Correct)

Similar documents based on text:   More   All
0.5:   Predictive Precharging for Bitline Leakage Energy.. - Kim, Vijaykrishnan.. (2002)   (Correct)
0.1:   A High Speed Wide Band SRAM Macro using Complementary.. - Yasunobu Nakase Harufusa   (Correct)
0.1:   An Accurate Power and Timing Modeling Technique Applied To A .. - Turier Ben Ammar (1998)   (Correct)

BibTeX entry:   (Update)

@misc{ kim-precharging,
  author = "Jong Min Kim",
  title = "Precharging Cache : A Context-Switch Robust Cache Organization",
  url = "citeseer.ist.psu.edu/kim94precharging.html" }
Citations (may not include all citations):
183   Profile guided code positioning (context) - Pettis, Hansen - 1990
126   The impact of operating system scheduling policies and synch.. (context) - Gupta, Tucker et al. - 1991
107   Achieving high instruction cache performance with an optimiz.. (context) - Hwu, Chang - 1989
94   The effect of context switches on cache performance (context) - Mogul, Borg - 1991
86   Cache performance of operating system and multiprogramming w.. (context) - Agarwal, Hennessy et al. - 1988
67   Page placement algorithms for large real-indexed caches - Kessler, Hill - 1992
58   Using processor-cache affinity information in shared-memory .. (context) - Squillante, Lazowska - 1990
51   Precision architecture (context) - Lee - 1989
33   Architecture of the pentium microprocessor (context) - Alpert, Avnon - 1993
21   BACH: BYU Address Collection Hardware (context) - Flanagan, Grimsrud et al. - 1992
9   Page allocation to reduce access time of physical caches (context) - Bray, Lynch et al. - 1990
4   Improving directed-mapped cache performance by the addition .. (context) - Jouppi - 1990
4   BACH: BYU Address Collection Hardware; The Collection of Com.. (context) - Flanagan, Nelson et al. - 1992
3   Evaluating the benefits of cache-affinity scheduling in shar.. (context) - Torrellas, Tucker et al. - 1992
1   microSPARC-II data sheet (context) - Microsystems - 1994
1   Digital's ALPHA Chip Project (context) - Supnik - 1993

Documents on the same site (http://realtime.snu.ac.kr/jmkim/):
Accepted for publication in Microprocessors and Microsystems. - Te Ms (1998)   (Correct)
A Low-Overhead High-Performance Unified Buffer.. - Kim, Choi, Kim.. (2000)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC