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Abstract: Recent architectures in academia and industry have explored placing multiple processors on a single chip, but a consensus has not emerged on the memory architecture. The recent availability of embedded DRAM (EDRAM) has further complicated the formula. In this investigation, we present a new and comprehensive comparison of four very different memory technologies in the same framework: SRAM cache, SRAM configured as pageable memory, EDRAM configured as cache, and EDRAM configured as pageable... (Update)
Context of citations to this paper: More
.... More recently, Keltcher et al. did an equal area comparison of embedded DRAM and SRAM memory architectures for a chip multiprocessor [18]. The authors fixed the percentage of die area devoted to on chip memory, and studied the impact of varying the die area devoted to L1 and...
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BibTeX entry: (Update)
P. Keltcher, S. Richardson, and S. Siu. An equal area comparison of embedded DRAM and SRAM memory architectures for a chip multiprocessor. Technical Report HPL-2000-53, Computer Systems Technology HP Laboratories Palo Alto, Apr 2000. http://citeseer.ist.psu.edu/keltcher00equal.html More
@misc{ keltcher00equal,
author = "P. Keltcher and S. Richardson and S. Siu",
title = "An equal area comparison of embedded DRAM and SRAM memory architectures
for a chip multiprocessor",
text = "P. Keltcher, S. Richardson, and S. Siu. An equal area comparison of embedded
DRAM and SRAM memory architectures for a chip multiprocessor. Technical
Report HPL-2000-53, Computer Systems Technology HP Laboratories Palo Alto,
Apr 2000.",
year = "2000",
url = "citeseer.ist.psu.edu/keltcher00equal.html" }
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