Arun Kejariwal, Xinmin Tian, Wei Li, Milind Girkar, Sergey Kozhukhov, Hideki Saito, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos  Home/Search
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Abstract: Recent research in thread-level speculation (TLS) has proposed several mechanisms for optimistic execution of di#cultto -analyze serial codes in parallel. Though it has been shown that TLS helps to achieve higher levels of parallelism, evaluation of the unique performance potential of TLS, i.e., performance gain that be achieved only through speculation, has not received much attention. In this paper, we evaluate this aspect, by separating the speedup achievable via true TLP (thread-level... (Update)
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BibTeX entry: (Update)
@misc{ kejariwal-performance,
author = "Arun Kejariwal and Xinmin Tian and Wei Li and Milind Girkar and Sergey
Kozhukhov and Hideki Saito and Utpal Banerjee and Alexandru Nicolau and
Alexander V. Veidenbaum and Constantine D. Polychronopoulos",
title = "On the Performance Potential of Different Types of Speculative Thread-Level
Parallelism",
url = "citeseer.ist.psu.edu/kejariwal06performance.html" }
Citations (may not include all citations):407 Trace Scheduling: A technique for global microcode compactio.. (context) - Fisher - 1981
299 Dependence Analysis for Supercomputing (context) - Banerjee - 1988
190 Value locality and load value prediction - Lipasti, Wilkerson et al. - 1996
159 The LRPD test: Speculative run-time parallelization of loops.. - Rauchwerger, Padua - 1995
103 Speculative execution based on value prediction - Gabbay, Mendelson - 1996
37 Run-time disambiguation: coping with statically unpredictabl.. (context) - Nicolau - 1989
17 The Optimization of Horizontal Microcode Within and Beyond B.. (context) - Fisher - 1979
8 Dynamic characteristics of loops (context) - Kobayashi - 1984
7 A controllable MIMD architectures (context) - Lundstrom, Barnes - 1980
7 Silent stores and store value locality (context) - Lepak, Bell et al. - 2001
7 A quantitative assessment of thread-level speculation techni.. - Marcuello, Gonzalez - 2000
6 Limits on speculative module-level parallelism in imperative.. - Warg, Stenstrom - 2001
5 Loop-level parallelism in numeric and symbolic programs (context) - Larus - 1993
2 Automatic detection of saturation and clipping idioms (context) - Bik, Girkar et al. - 2002
2 Speculative precomputation: Exploring the use of multithread.. (context) - Wang, Wang et al. - 2002
1 Speculative synchronization: Programmability and performance.. (context) - Martinez, Torrellas - 2003
1 IBM RISC system/6000 system architecture (context) - Oehler, Groves - 1990
1 Limits of data value predictability (context) - Sazeides, Smith - 1999
1 IBM Technical Disclosure Bulletin (context) - Jr, Wilner et al. - 1979
1 Automatic assignment of computations in a variable structure.. (context) - Estrin, Turn - 1963
1 IEEE Transactions on Parallel and Distributed Systems (context) - Vijaykumar, Gopal et al. - 2001
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