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Abstract: Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Smaller feature sizes have decreased the transistor switching time but at the same time increased the resistance of interconnect wires, resulting in slower signal transmission in on-chip wiring. Since future chips will have more silicon area and include more execution units, a much larger demand for parallelism is emerging. However,... (Update)
Context of citations to this paper: More
...exotic, huge size problems. Few existing architectures are able to take advantage of fine grain parallelism, although a recent study [8] shows that it is readily available even in common benchmark programs. Figure 1 1 (reproduced from pp.113 [8] courtesy of Stephen Keckler)...
...the inter cluster communication mechanisms to reduce the communication and synchronization overhead. This approach has been shown [18] [16] to be very effective, achieving noticably higher speedups then memory based communication on a number of fine grained applications. Figure...
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BibTeX entry: (Update)
Steve Keckler, "Fast Thread Communication and Synchronization Mechanisms for a Scalable Single Chip Multiprocessor", PhD. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1998. http://citeseer.ist.psu.edu/keckler98fast.html More
@misc{ keckler98fast,
author = "S. Keckler",
title = "Fast Thread Communication and Synchronization Mechanisms for a Scalable
Single Chip Multiprocessor",
text = "Steve Keckler, Fast Thread Communication and Synchronization Mechanisms
for a Scalable Single Chip Multiprocessor, PhD. Thesis, Department of Electrical
Engineering and Computer Science, Massachusetts Institute of Technology,
1998.",
year = "1998",
url = "citeseer.ist.psu.edu/keckler98fast.html" }
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