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Abstract: The technology to implement a single-chip node composed of 4 high-performance floating-point ALUs will be available by 1995. This paper presents processor coupling,a mechanism for controlling multiple ALUs to exploit both instruction-level and inter-thread parallelism, by using compile time and runtime scheduling. The compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting ... (Update)
Context of citations to this paper: More
...level to the process level. The 12 function units in a single M Machine node are controlled using a form of Processor Coupling [18] to exploit instruction level parallelism by executing 12 operations from the same thread, or to exploit thread level parallelism by...
...one thread to be filled by instructions from another. An extreme model of multithreading, variously proposed as processor coupling [Keckler92], parallel multithreading [Hirata92] and simultaneous multithreading [Tullsen95] allows multiple threads to issue instructions during...
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BibTeX entry: (Update)
Stephen W. Keckler and William J. Dally. Processor coupling: Integrating compile time and runtime scheduling for parallelism. In Proceedings of the 19th Annual International Symposium on Computer Architecture, pages 202--213, May 19--21, 1992. http://citeseer.ist.psu.edu/keckler92processor.html More
@inproceedings{ keckler92processor,
author = "Stephen W. Keckler and William J. Dally",
title = "Processor coupling: integrating compile time and runtime scheduling for parallelism",
booktitle = "Proceedings of the19th Annual International Symposium on Computer Architecture",
address = "Gold Coast, Australia",
pages = "202--213",
year = "1992",
url = "citeseer.ist.psu.edu/keckler92processor.html" }
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150 An efficient algorithm for exploiting multiple arithmetic un.. (context) - TOMASULO - 1967
130 A VLIW architecture for a trace scheduling compiler (context) - COLWELL, NIX et al. - 1988
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32 A variable instruction stream extension to the VLIW architec.. (context) - WOLFE, SHEN - 1991
25 Instruction-level parallel processing (context) - FISHER, RAU - 1991
22 The Horizon supercomputing system: Architecture and software (context) - KUEHN, SMITH - 1988
20 Architecture and implementation of a VLIW supercomputer (context) - COLWELL, HALL et al. - 1990
16 A mechanism for efficient context switching - NUTH, DALLY - 1991
13 Annual Reviews in Computer Science (context) - CULLER, architectures - 1986
4 Circuit simulation on shared memory multiprocessors (context) - SADAYAPPAN, VISVANATHAN - 1988
2 Von Neumann hybrid architecture (context) - IANUCCI, Toward - 1988
1 A coupled multi-ALU processing node for a highly parallel co.. - KECKLER - 1992
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