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Abstract: As the number of instructions executed in parallel increases, superscalar processors will require higher bandwidth from data caches. Because of the high cost of true multi-ported caches, alternative cache designs must be evaluated. The purpose of this study is to examine the data cache bandwidth requirements of high-degree superscalar processors, and investigate alternative solutions. The designs studied range from classic solutions like multi-banked caches to more complex solutions recently... (Update)
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...on performance, several simulations were run where cache access time is increased by one or two cycles. The results are reported in [JNT96] Nature of bank conflicts Bank conflicts are shown in Figure 6 which indicates the distribution of the number of simultaneous requests...
.... say 4 to 16, this is not feasible and alternative designs using multiple banks or hybrids of multi bank and multi port must be used [11, 12]. Thus, no obvious solution seems to be available for scaling current superscalar processors up to issuing four or more memory accesses...
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BibTeX entry: (Update)
T. Juan, J. J. Navarro, and O. Temam, "Data Caches for Superscalar Processors," Proceedings of ICS, July 1997. http://citeseer.ist.psu.edu/juan97data.html More
@inproceedings{ juan97data,
author = "Toni Juan and Juan J. Navarro and Olivier Temam",
title = "Data Caches for Superscalar Processors",
booktitle = "International Conference on Supercomputing",
pages = "60-67",
year = "1997",
url = "citeseer.ist.psu.edu/juan97data.html" }
Citations (may not include all citations):367 Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1996
110 Memory bandwidth limitations of future microprocessors - Burger, Kagi et al. - 1996
93 High-bandwidth data memory systems for superscalar processor.. (context) - Sohi, Franklin - 1991
75 Increasing the instruction fetch rate via multiple branch pr.. - Yeh, Marr et al. - 1993
72 Alpha Architecture Handbook (context) - Corporation, Massachussets - 1996
72 Alpha Architecture Handbook (context) - Corporation, Massachussets - 1994
71 An area model for on-chip memories and its application (context) - Mulder, Quach et al. - 1991
26 the effective bandwidth of interleaved memories in vector pr.. (context) - Oed, Lange - 1985
22 Increasing cache port efficiency for dynamic superscalar mic.. (context) - Wilson, Olukotun et al. - 1996
16 Exploring Configurations of Functional Units in an Out-of-Or.. - Jourdan, Sainrat et al. - 1995
12 Microprocessor Chip Set (context) - Incorporated - 1994
11 Highbandwidth address translation for multiple-issue process.. - Austin, Sohi - 1996
11 Distributed storage control unit for the hitachi s-3800 mult.. (context) - Kitai, Isobe et al. - 1994
10 SPA package (context) - Irlam - 1991
9 Performance characterization of the alpha 21164 microprocess.. - Cvetanovic, Bhandakar - 1996
7 Data caches for superscalar processors - Juan, Navarro et al. - 1996
4 Buffered banks in multiprocessor systems - Robbins, Robbins - 1995
2 HP-8000 combines complexity and speed (context) - Gwennap - 1994
1 IBM Regains Performance Lead with Power (context) - vol - 1993
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