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Abstract: Projections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on conventional caching techniques. This paper presents hardware techniques to improve the performance of caches. Miss caching places a small fully-associative cache between a cache and its refill path. Misses in the cache that hit in the miss cache... (Update)
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BibTeX entry: (Update)
Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 364--373. IEEE, June 1990. http://citeseer.ist.psu.edu/jouppi90improving.html More
@inproceedings{ jouppi98improving,
author = "Norman P. Jouppi",
title = "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers",
booktitle = "25 Years {ISCA}: Retrospectives and Reprints",
pages = "388-397",
year = "1998",
url = "citeseer.ist.psu.edu/jouppi90improving.html" }
Citations (may not include all citations):40 the Inclusion Properties for Multi-Level Cache Hierarchies (context) - Jean-Loup, Wenn-Hann - 1988
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