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Abstract: Monsoon is a parallel processing dataflow computer that will require a high bandwidth interconnection network. A packet switched routing chip (PaRC) is described that will be used as the basis of this network. PaRC is a 4 by 4 routing switch which has been designed and fabricated as a CMOS gate array. PaRC will receive packets via one of its four input ports, store the packet in an on-chip buffer, and eventually transmit the packet via one of its four output ports. PaRC operates at 50 MHz, and... (Update)
Context of citations to this paper: More
...requires a positive acknowledgement for buffer management or fault tolerance. Other mechanisms which provide hardware acknowledgements [36, 35] have been proposed, but they all consume substantial network bandwidth. 9 Summary We have presented Compressionless Routing, a...
...in previous schemes, each message requires a positive acknowledgement. Though other mechanisms which provide hardware acknowledgements [10, 11] have been proposed, they all consume substantial network bandwidth. 8 Summary In this paper, we have presented Compressionless...
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Arctic Routing Chip - Boughton (1994) (Correct)
Hardware Mechanisms for Efficient Interprocessor Communication - Henry (1996) (Correct)
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BibTeX entry: (Update)
Christopher F. Joerg. "Design and Implementation of a Packet Switched Routing Chip." MIT/LCS/TR-482, December 1990. http://citeseer.ist.psu.edu/joerg90design.html More
@techreport{ joerg90design,
author = "C. F. Joerg",
title = "{DESIGN} {AND} {IMPLEMENTATION} {OF} {A} {PACKET} {SWITCHED} {ROUTING} {CHIP}",
number = "MIT/LCS/TR-482",
pages = "119",
year = "1990",
url = "citeseer.ist.psu.edu/joerg90design.html" }
Citations (may not include all citations):156 Fat Trees: Universal Networks for Hardware-Efficient Superco.. (context) - Leiserson - 1985
144 Virtual Channel Flow Control (context) - Dally - 1990
121 Monsoon: An Explicit Token Store Architecture (context) - Papadopoulos, Culler - 1990
97 Communications of the ACM (context) - Seitz, Cube - 1985
53 Implementation of a General Purpose Dataflow Multiprocessor (context) - Papadopoulos - 1988
36 Connection Machine Model CM-2 Technical Summary (context) - Corporation - 1987
22 Prentice-Hall Inc (context) - Tanenbaum - 1988
22 Cube Microprocessor Array (context) - Pease, Binary - 1983
17 Massachusetts Institute of Technology (context) - Nikhil, Reference et al. - 1987
11 The Price of Asynchronous Parallelism: An Analysis of Datafl.. (context) - Arvind, Ekanadham - 1988
7 The Epsilon-2 Multiprocessor System (context) - Grafe, Hoch - 1990
3 The Design and Implementation of a Multi-Queue Buffer for VL.. - Frazier, Tamir - 1989
2 Massachusetts Institute of Technology (context) - Boughton, Chip et al. - 1989
2 Implementation of an I-Structure Memory Controller (context) - Steele - 1990
1 The Clock Distribution System of the Multiprocessor Emulatio.. - Younis - 1986
1 Design of a Packet Switched Routing Chip for the Dataflow Su.. (context) - Joerg - 1987
The graph only includes citing articles where the year of publication is known.
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