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Abstract: An important benefit of high-level synthesis is rapid design space exploration through examination of different design alternatives. However, such design space exploration is not feasible without fast and accurate area and delay estimates of the synthesized designs. These estimates must factor in physical design effects and technology-specific information in order to achieve accuracy. High-level synthesis tools often use abstract, parameterized component generators for describing the... (Update)
Context of citations to this paper: More
...error bound of 10 . In the rest of this section, we briefly describe the formulation of the models and the determination of the coefficients. [12] contains a detailed description of our approach. 3.2 Formulation of Estimation Models Recall that the area delay estimation models...
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BibTeX entry: (Update)
P. Jha and N. Dutt, "A Fast Area-Delay Estimation technique for RTL component generators," Technical Report 92-33, University of California at Irvine, April 1992. http://citeseer.ist.psu.edu/jha92fast.html More
@techreport{ jha92fast,
author = "Pradip K. Jha and Nikil Dutt",
title = "A Fast Area-Delay Estimation Technique for {RTL} Component Generators",
number = "ICS-TR-92-33",
pages = "33",
year = "1992",
url = "citeseer.ist.psu.edu/jha92fast.html" }
Citations (may not include all citations):217 High-Level Synthesis: Introduction to Chip and System Design (context) - Gajski, Dutt et al. - 1992
150 MIS : A multiple-level logic optimization system (context) - Brayton, Rudell et al. - 1987
34 The Synthesis Approach to Digital System Design (context) - Michel, Lauther et al. - 1992
21 Techniques for Area Estimation of VLSI Layouts (context) - Kurdahi, Parker - 1989
16 Synthesis from VHDL (context) - Lis, Gajski - 1988
13 Area-Time Model for Synthesis of Non-Pipelined Designs (context) - Jain, Mlinar et al. - 1988
11 Layout-Area Models for High-Level Synthesis (context) - C-H, Chaiyakul et al. - 1991 DBLP
11 Bridging High-Level Synthesis to RTL Technology Libraries (context) - Dutt, Kipps - 1991 ACM DBLP
10 An Algorithm for Component Selection in Performance Optimize.. (context) - Ramachandran, Gajski - 1991
8 Timing Models for High-level Synthesis (context) - Chaiyakul, C-H et al. - 1991 ACM
7 Computer Engineering Hardware Design (context) - Mano - 1988
7 How to Build a Hardware Description and Measurement System o.. (context) - Wolf
6 High-level Delay Estimation for TechnologyIndependent Logic .. (context) - Wallace, Chandrasekhar - 1990
6 GENUS:A Generic Component Library for High Level Synthesis (context) - Dutt - 1988
6 MOSP: Module Selection for Pipelined Designs with Multi-cycl.. (context) - Jain - 1990
5 LAST: A Layout Area and Shape function esTimator for High Le.. (context) - Kurdahi, Ramachandran - 1991
5 Constraint Driven Behavioral Synthesis (context) - Brewer - 1988 ACM
3 An Approach to Component Generation and Technology Adaption (context) - Kipps - 1991
3 Generic Component Library Characterization for High Level Sy.. (context) - Dutt - 1991
3 TELE: A Timing Evaluator using Layout Estimation for High Le.. (context) - Ramachandran, Kurdahi - 1992
2 Technology Independent Estimation of Area in Logic Synthesis (context) - Ji, Oh et al. - 1992
2 An Algebraic Model for Design Space with Applications to Fun.. (context) - Tyagi - 1990 ACM
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