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Abstract: Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due to capacity and compulsory misses. Trace preconstruction augments a trace cache by performing a function analogous to prefetching. The trace preconstruction mechanism observes the processor's instruction dispatch stream to detect opportunities for jumping ahead of the processor. After doing so, the preconstruction... (Update)
Context of citations to this paper: More
...by fetching other useful instructions while the miss is resolved. This mechanism can be thought of as just in time trace constructor [8] that can build multiple traces concurrently. We also observed that programs display a remarkably large amount of trace locality. In some...
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BibTeX entry: (Update)
Q. Jacobson and J. E. Smith. Trace Preconstruction. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 37--46, Vancouver, British Columbia, June 12--14, 2000. http://citeseer.ist.psu.edu/jacobson00trace.html More
@inproceedings{ jacobson00trace,
author = "Quinn Jacobson and James E. Smith",
title = "Trace preconstruction",
booktitle = "{ISCA}",
pages = "37-46",
year = "2000",
url = "citeseer.ist.psu.edu/jacobson00trace.html" }
Citations (may not include all citations):241 A Study of Branch Prediction Strategies (context) - Smith - 1981
183 Trace Cache: a Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Bennett et al. - 1996
177 Evaluating Future Microprocessors: The SimpleScalar Tool Set - Burger, Austin et al. - 1996
125 Trace Processors - Rotenberg, Jacobson et al. - 1997
109 Comparative Evaluation of Latency Reducing and Tolerating Te.. - Gupta, Hennessy et al. - 1991
72 A Dynamic Multithreading Processor - Akkary, Driscoll - 1998
39 Path-Based Next Trace Prediction - Jacobson, Rotenberg et al. - 1997
37 Putting the Fill Unit to Work: Dynamic Optimizations for Tra.. - Friendly, Patel et al. - 1998
37 Critical Issues Regarding the Trace Cache Fetch Mechanism - Patel, Friendly et al. - 1997
36 Sequential Program Prefetching in Memory Hierarchies (context) - Smith - 1978
34 Prefetching in Supercomputer Instruction Caches (context) - Smith, Hsu - 1992
26 Instruction Pre-Processing in Trace Processors - Jacobson, Smith - 1999
23 ARB: A Hardware Mechanism for Dynamic Memory Disambiguation (context) - Franklin, Sohi - 1996
10 An Intelligent I-Cache Prefetch Mechanism (context) - Young, Shekita - 1993
1 High-Performance Frontends for Trace Processors - Jacobson - 1999
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