Yerang Hur, Young Hyun Bae, Sung-Soo Lim, Sung-Kwan Kim, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Minsuk Lee  Home/Search
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Abstract: This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing schema provides means to reason about the execution time variation of a program construct by surrounding program constructs due to pipelined... (Update)
Context of citations to this paper: More
.... [7, 22, 21] to optimized programs on pipelined RISC processors [9, 17, 28] and from uncached architectures to instruction caches [3, 11, 15]. However, there has been little previous work on predicting WCET for data caching. Only three previous attempts have been reported....
.... can calculate safe, tight WCET bounds for tasks executing on single issue inorder pipelines with instruction and data caches [2,11,12,14,15,16,17,18,26,34,42]. However, the level of sophistication needed to safely and accurately analyze more complex architectures is formidable....
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BibTeX entry: (Update)
Y. Hur, Y. H. Bea, S.-S. Lim, B.-D. Rhee, S. L. Min, Y. C. Park, M. Lee, H. Shin, and C. S. Kim. Worst case timing analysis of risc processors: R3000/R3010 case study. In IEEE Symposium on Real-Time Systems, pages 308--319, December 1995. http://citeseer.ist.psu.edu/hur95worst.html More
@inproceedings{ hur95worst,
author = "Yerang Hur and Young Hyun Bae and Sung-Soo Lim and Sung-Kwan Kim and Byung-Do Rhee and Sang Lyul Min and Chang Yun Park and Heonshik Shin and Chong Sang Kim",
title = "Worst Case Timing Analysis of {RISC} Processors: R3000/R3010 Case Study",
booktitle = "{IEEE} Real-Time Systems Symposium",
pages = "308-321",
year = "1995",
url = "citeseer.ist.psu.edu/hur95worst.html" }
Citations (may not include all citations):1575 Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1990
1399 Compilers Principles (context) - Aho, Sethi et al. - 1988
222 MIPS RISC Architecture (context) - Kane, Heinrich - 1992
167 Calculating the Maximum Execution Time of Real-Time Programs (context) - Puschner, Koza - 1989
103 Experiments with a Program Timing Tool Based on Source-Level.. (context) - Park, Shaw - 1990
102 A Characterization of the Minimum Cycle Mean in a Digraph (context) - Karp - 1978
97 The Architecture of Pipelined Computers (context) - Kogge - 1981
92 Reasoning About Time in Higher-Level Language Software - Shaw - 1989
85 Predicting Program Execution Times by Analyzing Static and D.. (context) - Park - 1993
63 A Code Generation Interface for ANSI C - Fraser, Hanson - 1990
31 An Accurate Worst Case Timing Analysis Technique for RISC Pr.. - Lim, Bae et al. - 1994
28 Cummings Publishing Company (context) - Fischer, LeBlanc et al. - 1991
15 Retargetable Instruction Scheduling for Pipelined Processors - Bradlee - 1991
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