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Abstract: od. A cycle-stealing DMA I/O task is allowed to proceed only when the CPU does not need the system bus. As a result, the execution time of a cycle-stealing DMA I/O task is affected by a set of CPU tasks which execute concurrently with the I/O task. We discuss the problem of bounding the WCET of a cycle-stealing DMA I/O task under a workload which consists of a set of independent CPU tasks. Each CPU task has an arbitrary release time. We use the dynamic programming technique to bound the WCET of ... (Update)
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BibTeX entry: (Update)
T.-Y. Huang, "Worst-case timing analysis of concurrently executing DMA I/O and programs," Ph.D. dissertation, Univ. Illinois, Dept. Computer Sci., Sept. 1996. http://citeseer.ist.psu.edu/huang97worstcase.html More
@techreport{ huang96worstcase,
author = "Tai-Yi Huang",
title = "Worst-Case Timing Analysis of Concurrently Executing {DMA} {I}/{O} and Programs",
number = "UIUCDCS-R-96-1978",
year = "1996",
url = "citeseer.ist.psu.edu/huang97worstcase.html" }
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