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Abstract: Hard-real-time schedulability analysis is carried out based on the assumption that the worst-case execution time (WCET) of each task is known. Cyclestealing Direct Memory Access (DMA) I/O steals bus cycles from an executing program and prolongs the execution time of the program. Because of the difficulty in bounding the interference on the executing program, cycle-stealing DMA I/O is often disabled in hard-real-time systems. This paper presents an analytical method for bounding the WCET of a... (Update)
Active bibliography (related documents): More All
0.4: Worst Case Timing Analysis Of Concurrently Executing Dma I/o And.. - Huang (1997) (Correct)
0.3: A Method for Bounding the Effect of DMA I/O Interference on.. - Huang, Liu, Hull (1996) (Correct)
0.3: Worst-Case Timing Analysis of Concurrently Executing DMA I/O and.. - Huang (1997) (Correct)
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BibTeX entry: (Update)
@inproceedings{ huangallowing,
author = "T.-Y. Huang and J. W.-S. Liu and J.-Y. Chung",
title = "Allowing Cycle-Stealing Direct Memory Access {I/O} Concurrent with Hard-Real-Time Programs",
pages = "422--429",
url = "citeseer.ist.psu.edu/huang96allowing.html" }
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31 An accurate worst case timing analysis technique for RISC pr.. - Lim - 1994
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13 Predicting program execution times by analyzing static and d.. (context) - Park - 1993 ACM DBLP
11 Correlation analysis techniques for refining execution time .. - Gupta, Gopinath - 1994
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