(Enter summary)
Abstract: This paper describes an efficient algorithm which gives a
bound on the worst-case execution times of the concurrent
execution of CPU instructions and cycle-stealing
DMA I/O operations. Simulations of several programs
were conducted to evaluate this algorithm. Compared
with the traditional pessimistic approach, the bound
on the worst-case execution time produced by the algorithm
is significantly tighter. For a sample program
that multiplies two matrices while the I/O bus is fully
utilized, our... (Update)
Context of citations to this paper: More
...197.20 2071.10 Table 7: Execution times with without dynamic path analysis 8. 7 WCET When Cycle Stealing DMA is Used Huang and Liu [HL95], have investigated WCET when cycle stealing DMA is used. DMA stand for direct memory access. A DMA controller transfers data between the...
...interrupts, DMA transfers, and operating system overheads. DMA transfers result in bus arbitration overheads, even in cycle stealing mode [7]. Operating system overheads consist mainly of context switching times in multitasking operating systems. An architectural solution to...
Cited by: More
Allowing Cycle-Stealing Direct Memory Access I/O Concurrent.. - Huang, al. (1996)
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A Method for Bounding the Effect of DMA I/O Interference on.. - Huang, Liu, Hull (1996)
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Issues in using Heterogeneous HPC Systems for Embedded Real .. - Bhat, Lim, Prasanna (1995)
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Active bibliography (related documents): More All
0.5: Worst-Case Timing Analysis of Concurrently Executing DMA I/O and.. - Huang (1997)
(Correct)
0.3: Worst-Case Timing Analysis of Cycle-Stealing DMA I/O Tasks - Huang, Liu
(Correct)
0.3: Worst Case Timing Analysis Of Concurrently Executing Dma I/o And.. - Huang (1997)
(Correct)
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0.1: A Machine-Independent DMA Framework for NetBSD - Thorpe (1998)
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3: Calculating the maximum execution times of realtime programs (context) - Puschner, Koza - 1989
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BibTeX entry: (Update)
T. Huang and J. W.-S. Liu. Predicting the Worst-Case Execution Time of the Concurrent Execution of Instructions and Cycle-Stealing DMA I/O Operations. Workshop on Languages, Compilers and Tools for Real-Time Systems, June 1995. http://citeseer.ist.psu.edu/huang95predicting.html More
@inproceedings{ huang95predicting,
author = "Tai-Yi Huang and Jane W.-S. Liu",
title = "Predicting the Worst-Case Execution Time of the Concurrent Execution of Instructions and Cycle-Stealing {DMA} I/O Operations",
booktitle = "Workshop on Languages, Compilers, & Tools for Real-Time Systems",
pages = "1-6",
year = "1995",
url = "citeseer.ist.psu.edu/huang95predicting.html" }
Citations (may not include all citations):
167
Calculating the maximum execution time of real--time program.. (context) - Puschner, Koza - 1989
55
Pipelined processors and worst case execution times
- Zhang, Burns et al. - 1993
54
Evaluating tight execution time bounds of programs by annota.. (context) - Mok, Amerasinghe et al. - 1989
24
Predicting instruction cache behavior
- Mueller, Whalley et al. - 1994
21
Program representation and translation for predictable real-..
- Niehaus - 1991
19
Experiments with a program timing tool based on source-level.. (context) - Park, Shaw - 1991
13
Predicting program execution times by analyzing static and d.. (context) - Park - 1993
4
output paradigms for real-time systems (context) - Klein, Ralya et al. - 1990
1
the feasibiity of response time predictions--an experimental.. (context) - Vrchoticky, Puschner - 1991
Documents on the same site (http://www.cs.umd.edu/projects/TimeWare/sigplan95/): More
Static Timing Analysis of Real-Time Systems - Jourdan, Maraninchi (1995)
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Automatic Generation of Scheduling and Communication Code .. - Bakkers, Sunter, Ploeg (1995)
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Compiler Support for Software-Based Cache Partitioning - Mueller (1995)
(Correct)
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