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Abstract: The instruction window is a critical component and a major energy consumer in out-of-order superscalar processors. An important source of energy consumption in the instruction window is the instruction wakeup: a completing instruction broadcasts its result register tag and an associative comparison is performed with all the entries in the window. (Update)
Context of citations to this paper: More
.... also depends on the optimizations that could already be implemented within the issue queue, for example, the ones suggested in [3] and [8]. 6. Concluding Remarks Traditional comparators used in several datapath artifacts of a modern processor are notoriously energy...
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3: EnergyEffective Issue Logic (context) - Folegnani, Gonzalez - 2001
2: Quantifying the complexity of superscalar processors - Palacharla, Jouppi et al. - 1996
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BibTeX entry: (Update)
Huang, M., Renau, J., Torrellas, J., "Energy--Efficient Hybrid Wakeup Logic", in Proc. ISLPED, August 2002. http://citeseer.ist.psu.edu/huang02energyefficient.html More
@inproceedings{ huang.islped02,
author = "M. Huang and J. Renau and J. Torrellas",
title = "{Energy-Efficient Hybrid Wakeup Logic}",
booktitle = "International Sysmposim on Low-Power Electronics and Design",
month = "August",
year = "2002",
pages = "196--201",
address = "Monterey, California",
url = "citeseer.ist.psu.edu/huang02energyefficient.html" }
Citations (may not include all citations):175 Complexity Effective Superscalar Processors - Palacharla, Jouppi et al. - 1997
136 Superscalar Microprocessor (context) - Yeager - 1996
40 Power and Energy Reduction Via Pipeline Balancing (context) - Bahar, Manne - 2001
33 Energy-Effective Issue Logic (context) - Folegnani, Gonzalez - 2001
29 Instruction Issue Logic in Pipelined Supercomputers - Weiss, Smith - 1984
18 Reducing Power Requirements of Instruction Scheduling Throug.. - Ponomarev, Kucuk et al. - 2001
17 A Low-Complexity Issue Logic (context) - Canal, Gonzalez - 2000
17 A Direct Execution Framework for Fast and Accurate Simulatio.. - Krishnan, Torrellas - 1998
15 Select-Free Instruction Scheduling Logic - Brown, Stark et al. - 2001
12 Optimization of High-Performance Superscalar Architectures f.. (context) - Zyuban, Kogge - 2000
5 Reducing Energy Requirements for Instruction Issue and Dispa.. (context) - Ghose - 2000
4 A High-Speed Dynamic Instruction Scheduling Scheme for Super.. (context) - Goshima, Nishino et al. - 2001
4 Superscalar Execution With Dynamic Data Forwarding - Onder, Gupta - 1998
3 Issue Logic for a 600-MHz Out-ofOrder Execution Microprocess.. (context) - Farrell, Fischer - 1996
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Cherry: Checkpointed Early Resource Recycling in.. - Martinez, Renau.. (2002) (Correct)
Profile-Based Energy Reduction for High-Performance Processors - Huang, Renau, Torrellas (2001) (Correct)
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