Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos  Home/Search
Context Related
| utexas.edu/users/d...witz_signaling.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: utexas.edu/users/dburger/teach... (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: this article, we examine the limitations of CMOS implementations of highspeed links and show that the links' performance should continue to scale with technology. To handle the interconnects' finite bandwidth, however, requires more sophisticated signaling methods. CMOS circuits, typically slower than circuits implemented in nonmainstream technologies, are particularly attractive for common applications because of their lower cost. The overall system cost is further reduced when signaling... (Update)
Cited by: More
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE.. - Nagarajan, etal. (2004) (Correct)
Surfing: A Robust Form of Wave Pipelining Using Self-Timed .. - Winters, Greenstreet (Correct)
A High-Speed Clockless Serial Link Transceiver - John Teifel And (Correct)
Similar documents (at the sentence level):
19.3%: High Speed Electrical Signalling: Overview and Limitations - Horowitz, Yang, Sidiropoulos (1998) (Correct)
Active bibliography (related documents): More All
3.3: Design of High-Speed Serial Links in CMOS - Yang (1998) (Correct)
0.7: High Performance Inter-Chip Signalling - Sidiropoulos (1998) (Correct)
0.5: Data Converters for High Speed CMOS Links - Ellersick (2001) (Correct)
Similar documents based on text: More All
0.2: A 2.4 Gb/s/pin Simultaneous Bidirectional Parallel Link with.. - Yeung (2000) (Correct)
0.1: 8 Gbps CMOS interface for parallel fiber-optic interconnects - Sano, Madhavan, Levi (Correct)
0.1: A Signaling System Using Lightweight Call Sessions - Wang, Joseph, Katz (2000) (Correct)
Related documents from co-citation: More All
4: Digital Systems Engineering (context) - Dally, Pulton - 1998
3: High-Speed Compact Circuits with CMOS (context) - Krambeck, Lee et al. - 1982
3: Logical Effort: Designing Fast CMOS Circuits (context) - Sutherland, Sproull et al. - 1999
BibTeX entry: (Update)
Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos, "High-speed Electrical Signaling: Overview and Limitations", in IEEE Micro, January/February 1998, pp.12--24. http://citeseer.ist.psu.edu/horowitz98highspeed.html More
@article{ horowitz98highspeed,
author = "M. Horowitz and C. K. K. Yang and S. Sidiropoulos",
title = "High-Speed Electrical Signaling --- Overview and Limitations",
journal = "IEEE Micro",
volume = "18",
number = "1",
month = "\slash",
pages = "12--24",
year = "1998",
url = "citeseer.ist.psu.edu/horowitz98highspeed.html" }
Citations (may not include all citations):61 Matching Properties of MOS Transistors (context) - Pelgrom - 1989
46 Communication Systems Engineering (context) - Proakis, Salehi - 1994 ACM
31 Precise Delay Generation Using Coupled Oscillators - Maneatis - 1993 ACM
26 Low-Jitter Process-Independent DLL and PLL Based on Self-Bia.. (context) - Maneatis - 1996
23 A Variable Delay Line PLL for CPUCoprocessor Synchronization (context) - Johnson - 1988
18 Charge-Pump Phase-Lock Loops (context) - Gardner - 1980
16 Integrated Analog-to-Digital and Digital-toAnalog Converters (context) - Plassche - 1994
15 Transmission Lines for Digital and Communication Networks (context) - Matick - 1997
13 Design of PLL-Based Clock Generation Circuits (context) - Jeong - 1987
10 Phase-Locked Loops (context) - Best - 1997
9 A CMOS Serial Link for Fully Duplexed Data Communication (context) - Lee - 1995
9 Monolithic Phase Locked Loops and Clock Recovery Circuits (context) - Razavi - 1996
9 A 1.0625 Gbps Transceiver with 2xOversampling and Transmit S.. (context) - Fiedler - 1997
7 A CMOS 8-Bit High Speed A/D Converter IC (context) - Yukawa
6 Technical Aspects of Data Communication (context) - McNamara - 1982 ACM
6 A Semi-Digital DLL with Unlimited Phase Shift Capability and.. (context) - Sidiropoulos - 1997
5 The Delay Vernier Pattern Generation Technique (context) - Moyer - 1997
5 A 900 Mb/s Bidirectional Signaling Scheme (context) - Mooney - 1995
4 Transmitter Equalization for 4-Gbps Signaling (context) - Dally - 1997 ACM
4 A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-m.. (context) - Kim - 1990
4 A 500-Megabyte/s Data Rate 4.5 M DRAM (context) - Kushiyama - 1993
4 A 0.6-m CMOS 4-Gbps Transceiver with Data Recovery using Ove.. (context) - Yang
3 A 700-Mb/s/pin CMOS Signaling Interface Using Current Integr.. (context) - Sidiropoulos - 1997
3 A 320 MHz CMOS Triple 8 bit DAC with PLL (context) - Reynolds - 1994
3 The Facts about FireWire [serial communication bus (context) - Wickelgren - 1997
3 NRZ Timing Recovery Technique for Band Limited Channels (context) - Song - 1996
3 Work Progresses on Gigabit Ethernet (context) - Thompson - 1997 ACM DBLP
3 A Second-Generation Modem Analog FrontEnd (context) - Combe - 1992
3 A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder (context) - Black - 1997
2 A 2Gb/s Asymmetric Link for High-Bandwidth Packet Switches (context) - Chang
1 A 200M Sample/s 6b Flash ADC in 0.6mm CMOS (context) - Spalding
1 An Equalization Scheme for 10Gb/s 4-PAM Signaling over Long .. (context) - Farjad-Rad - 1997
1 A 0.8-mm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter.. (context) - Yang - 1996
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.cs.utexas.edu/users/dburger/teaching/spring99/cs395t/): More
Exploiting Fine-Grain Thread Level Parallelism on.. - Keckler, Dally.. (1998) (Correct)
Industrial Economics and Strategy: Computing Platforms - Greenstein (1998) (Correct)
Starfire: Extending the SMP Envelope - Charlesworth (1998) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC