Technology mapping problems arize in logic synthesis systems, when the gap between a synthesized boolean network and the implementation of that network within a given target technology has to be bridged. This paper presents a modular, versatile technology mapping system that supports many different target technologies. Guided by a complexity analysis of the problem, we develop a variety of efficient, exact or heuristic methods for technology driven network clustering. Depending on the target technology and optimization methods and goals, different subnetworks must be provided as candidates for clustering. Methods to achieve this are also included. We conclude with experimental results we obtained with several configurations of the system for different target technologies. 1
|
218
|
FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs
– Cong, Ding
- 1994
|
|
207
|
Logic synthesis and optimization benchmarks user guide version
– Yang
- 1991
|
|
67
|
Dag-map: Graph-based FPGA technology mapping for delay optimization
– CHEN, CONG, et al.
- 1992
|
|
63
|
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
– Cong, Ding
- 1994
|
|
61
|
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs
– Francis, Rose, et al.
- 1991
|
|
49
|
Bdd based decomposition of logic for functions with applications to FPGA synthesis
– Lai, Pedram, et al.
- 1993
|
|
46
|
Chortle: A technology mapping program for lookup table based field programmable gate arrays
– Francis, Chung
- 1990
|
|
43
|
Performance-oriented technology mapping
– Touati
- 1990
|
|
42
|
Technology Mapping of Lookup Table-Based FPGAs for Performance
– Francis, Rose, et al.
- 1991
|
|
39
|
Code generation for expressions with common subexpressions
– Aho, Johnson, et al.
- 1977
|
|
39
|
Xmap: A technology mapper table-lookup field-programmable gate arrays
– KARPLUS
- 1991
|
|
39
|
Improved logic synthesis algorithms for table look up architectures
– Murgai
- 1991
|
|
33
|
Module clustering to minimize delay in digital networks
– Lawler, Levitt, et al.
- 1969
|
|
31
|
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays
– Murgai, Shenoy, et al.
- 1991
|
|
31
|
The transduction method—Design of logic networks based on permissible functions
– Muroga, Kambayashi, et al.
- 1989
|
|
29
|
Optimal Technology Mapping for Single Output Cells
– Kolla
- 1994
|
|
28
|
Logic Synthesis for Programmable Gate Arrays
– Murgai, Nishizaki, et al.
- 1990
|
|
27
|
Technology mapping in MIS
– Detjens, Gannot, et al.
- 1987
|
|
27
|
Functional multiple-output decomposition: Theory and an implicit algorithm,” in
– Wurth, Eckl, et al.
- 1995
|
|
25
|
Technology Mapping Using Boolean Matching and Don’t Care Sets
– Mailhot, Micheli
- 1990
|
|
24
|
Code generation for a one-register machine
– Bruno, Sethi
- 1976
|
|
20
|
Synthesis and optimization of digital circuits (McGrawHill
– Micheli
- 1994
|
|
20
|
Permutation and phase independent Boolean comparison
– Mohnke, Malik
- 1993
|
|
17
|
Optimum functional decomposition using encoding
– Murgai, Brayton, et al.
- 1994
|
|
13
|
Technology Binding and Local Optimization by DAG Matching
– DAGON
- 1987
|
|
10
|
Matching a Boolean Function against a Set of Functions
– Hinsberger, Kolla
- 1997
|
|
10
|
GAFAP: genetic algorithm for FPGA technology mapping
– Kommu, Pomenraz
- 1993
|
|
10
|
Boolean matching in logic synthesis
– SAVOJ, SILVA, et al.
- 1992
|
|
9
|
On Area/Depth Trade-Off
– Cong, Ding
- 1993
|
|
9
|
Approximative Representation of boolean Functions by size controllable ROBDD's
– Kunjan, Hinsberger, et al.
- 1997
|
|
8
|
Efficient computing communication complexity for multilevel logic synthesis
– Hwang, Owens, et al.
- 1992
|
|
8
|
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping
– Shen, Huang, et al.
- 1995
|
|
8
|
A method for finding good Ashenhurst decompositions and its application to FPGA synthesis
– Stanion, Sechen
- 1995
|
|
7
|
Communication Based Multilevel Synthesis for Multioutput Boolean Functions
– Molitor, Scholl
- 1994
|
|
6
|
A cell-based approach to performance optimization of fanout-free circuits
– Hinsberger, Kolla
- 1992
|
|
5
|
Exploiting communication complexity for multi-level logic synthesis
– Hwang, Owens, et al.
- 1990
|
|
5
|
Area and delay mapping for table-look-up based field programmable gate arrays
– SAWKAR, THOMAS
- 1992
|
|
4
|
Cell based Performance Optimization of Combinational Circuits
– Hinsberger, Kolla
- 1990
|
|
3
|
MIS: Multiplelevel interactive logic minimization
– Brayton, Rudell, et al.
- 1987
|
|
2
|
Bestimmung geeigneter Teilnetzwerke zur Realisierung kombinatorischer Logik in FPGAs
– Salazar
- 1993
|
|
1
|
Multi-Level Logic Synthesis Using Communication Complexity
– Hwang, Owens, et al.
- 1989
|
|
1
|
Berechnung lokaler Don't Cares in booleschen Netzwerken. Master 's thesis, Universit"at W"urzburg
– Kunjan
- 1997
|
