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Formal Synthesis for Pipeline Design (1999)  (Make Corrections)  (3 citations)
Holger Hinrichsen, Hans Eveking, Gerd Ritter



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Abstract: A method of formally correct synthesis is presented and applied to the automatic construction of pipelined processors. The approach is based on a small set of correctness-preserving transformations that are efficiently cross-checked by an independent formal verification tool. Basic pipeline strategies as well as automatic post-synthesis verification are provided. 1 (Update)

Context of citations to this paper:   More

...algorithmic descriptions. Currently it is used to perform intervening simplifications in our advanced automatic scheduling approach [HER99]. However, the independent implementation permits other applications. This paper presents new techniques for the simplification of acyclic...

.... from Microchip [11] The implementations have been generated automatically from the specifications using the synthesis tool described in [9]. Verification of the pipelined designs was done using the flushing approach of [5] see also [13] Tab. 1 gives the verification time,...

Cited by:   More
Sequential Equivalence Checking by Symbolic Simulation - Ritter   (Correct)
Formal Verification of Descriptions with Distinct Order .. - Ritter, Hinrichsen..   (Correct)
False-Path Elimination And Simplification Of Sequential .. - Hinrichsen, Ritter.. (2000)   (Correct)

Active bibliography (related documents):   More   All
0.7:   Formally Correct Construction of Pipelined Processors - Eveking, Hinrichsen, Ritter (1998)   (Correct)
0.5:   Formal Sequential Equivalence Checking of Digital Systems by.. - Ritter   (Correct)
0.0:   Formal Hardware Verification By Symbolic Trajectory Evaluation - Jain (1997)   (Correct)

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0.5:   Formal Verification of Designs with Complex Control by .. - Ritter, Eveking.. (1999)   (Correct)
0.1:   Verifying Parameterized Recursive Circuits Using.. - Hotz, Zhu (1997)   (Correct)
0.1:   Formal Synthesis in Circuit Design - A Classification .. - Kumar, Blumenröhr.. (1996)   (Correct)

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3:   Formal verification of designs with complex control by symbolic simulation - Ritter, Eveking et al. - 1999
3:   Computer Architecture: a Quantitative Approach (context) - Hennessy, Patterson - 1996
3:   A decision procedure for bit-vector arithmetic - Barrett, Dill et al. - 1998

BibTeX entry:   (Update)

H. Hinrichsen, H. Eveking, and G. Ritter. Formal synthesis for pipeline design. In Proc. DMTCS+CATS'99. Springer DMTCS, 1999. http://citeseer.ist.psu.edu/hinrichsen99formal.html   More

@misc{ hinrichsen99formal,
  author = "H. Hinrichsen and H. Eveking and G. Ritter",
  title = "Formal synthesis for pipeline design",
  text = "H. Hinrichsen, H. Eveking, and G. Ritter. Formal synthesis for pipeline
    design. In Proc. DMTCS+CATS'99. Springer DMTCS, 1999.",
  year = "1999",
  url = "citeseer.ist.psu.edu/hinrichsen99formal.html" }
Citations (may not include all citations):
1726   Graph-Based Algorithms for Boolean Function Manipulation - Bryant - 1986
1575   Computer Architecture: a Quantitative Approach (context) - Hennessy, Patterson - 1996
100   Automatic verification of pipelined microprocessor control - Burch, Dill - 1994
53   Sehwa: a software package for synthesis of pipelines from be.. (context) - Park, Parker - 1988
49   Path-Based Scheduling for Synthesis (context) - Camposano - 1991
48   Techniques for verifying superscalar microprocessors (context) - Burch - 1996
36   Analysis of programs for parallel processing (context) - Bernstein - 1966
34   The synthesis approach to digital system design (context) - Michel, Lauther et al. - 1992
16   Inverting the abstraction mapping: a methodology for hardwar.. - Cyrluk
15   Formal synthesis in circuit design - a classification and su.. - Kumar, Blumenrohr et al. - 1996
12   A Practical Method for Rigorously Controllable Hardware Desi.. - Borger, Mazzanti - 1997
2   Formally correct construction of a pipelined DLX architectur.. (context) - Hinrichsen - 1998
2   Formally Correct Construction of Pipelined Processors - Eveking, Hinrichsen et al. - 1998
1   Automata theory and formal microprogram transformations (context) - Glushko - 1965

Documents on the same site (http://www.rs.e-technik.tu-darmstadt.de/~gerd/publications.htm):   More
Formally Correct Construction of Pipelined Processors - Eveking, Hinrichsen, Ritter (1998)   (Correct)
False-Path Elimination And Simplification Of Sequential .. - Hinrichsen, Ritter.. (2000)   (Correct)
Formal Sequential Equivalence Checking of Digital Systems by.. - Ritter   (Correct)

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