John Heinlein, Robert P. Bosch, Jr., Kourosh Gharachorloo, Mendel Rosenblum, Anoop Gupta  Home/Search
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Abstract: A key goal of the Stanford FLASH project is to explore the integration of multiple communication protocols in a single multiprocessor architecture. To achieve this goal, FLASH includes a programmable node controller called MAGIC, which contains an embedded protocol processor capable of implementing multiple protocols. In this paper we present a specialized protocol for block data transfer integrated with a conventional cache coherence protocol. Block transfer forms the basis for message passing ... (Update)
Context of citations to this paper: More
...the message layer to send and receive coherence packets. In addition to message passing, Flash supports cache coherent block transfer [9]. In an evaluation of the performance of block transfer in Flash, Woo et al. reported limited benefit for the applications studied [20]...
.... Mechanisms 23 customized to implement various protocols, including a coherent block transfer protocol developed by Heinlein et al. [43]. Their implementation performs a line by line transfer of data from one memory location to another, maintaining global coherence with...
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3: The Stanford FLASH Multiprocessor (context) - Kuskin - 1994
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BibTeX entry: (Update)
J. Heinlein, K. Gharachorloo, R.P. Bosch, M. Rosenblum and A. Gupta. Coherent Block Data Transfer in the FLASH Multiprocessor. In Proceedings of the International Parallel Processing Symposium. 1997. http://citeseer.ist.psu.edu/heinlein97coherent.html More
@inproceedings{ heinleincoherent,
author = "J. Heinlein and K. Gharachorloo and R. {Bosch, Jr.} and M. Rosenblum and A. Gupta",
title = "Coherent Block Data Transfer in the {FLASH} Multiprocessor",
pages = "18--27",
url = "citeseer.ist.psu.edu/heinlein97coherent.html" }
Citations (may not include all citations):362 The Stanford FLASH Multiprocessor (context) - Kuskin, Ofelt et al. - 1994
357 The Directory-Based Cache Coherence Protocol for the DASH Mu.. (context) - Lenoski, Laudon et al. - 1990
275 Virtual Memory Mapped Network Interface for the SHRIMP Multi.. - Blumrich, Li et al. - 1994
268 Tempest and Typhoon: User-level Shared Memory - Reinhardt, Larus et al. - 1994
249 Tolerating Latency Through Software-Controlled Prefetching i.. - Mowry, Gupta - 1991
212 The MIT Alewife Machine: Architecture and Performance - Agarwal, Bianchini et al. - 1995
119 Document for a Standard Message-Passing Interface - Interface - 1993
91 Impact of Architectural Trends on Operating System Performan.. (context) - Rosenblum, Bugnion et al. - 1995
63 Complete Computer Simulation: The SimOS Approach (context) - Rosenblum, Herrod et al. - 1995
59 Operating System Support for Improving Data Locality on CC-N.. (context) - Verghese, Devine et al. - 1996
51 Anatomy of a Message in the Alewife Multiprocessor - Kubiatowicz, Agarwal - 1993
44 Early Experience with Message-Passing on the SHRIMP Multicom.. - Felten, Alpert et al. - 1996
43 Hive: Fault Containment For Shared-Memory Multiprocessors (context) - Chapin, Rosenblum et al. - 1995
41 Integration of Message Passing and Shared Memory in the Stan.. - Heinlein, Gharachorloo et al. - 1994
16 Memory System Performance of UNIX on CC-NUMA Multiprocessors (context) - Chapin, Herrod et al. - 1995
9 Cray TD System Architecture (context) - Research, System - 1993
6 The UltraSPARC Processor -- Technology White Paper (context) - Microsystems
2 Microprocessor User's Manual (context) - Graphics, MIPS - 1995
1 Argonne National Lab Tech Report (context) - Gropp, Lusk et al.
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