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Abstract: The use of automatic model checking algorithms to verify detailed gate or switch level designs of circuits is very attractive because the method is automatic and such models can accurately capture detailed functional, timing, and even subtle electrical behaviour of circuits. The use of binary decision diagrams has extended by orders of magnitude the size of circuits that can be so verified, but there are still very significant limitations due to the computational complexity of the problem.... (Update)
Context of citations to this paper: More
.... m so that g = m(h) then we can deduce that m(p) holds (and this can, in turn, be used for further reasoning) For more details see [3, 4] The problem posed in this paper is, in general, undecidable since we need to reason about arithmetic. However, it is possible to build...
...studied. For example, 8] used a three valued logic for interpreting results of model checking with abstract interpretation, whereas [16, 17] used four valued logics for reasoning about abstractions of detailed gate or switch level designs of circuits. Different multi valued...
Cited by: More
Model-Checking Over Multi-Valued Logics - Chechik, Easterbrook, Petrovykh (2001) (Correct)
Model Checking with Multi-Valued Temporal Logics - Chechik, Easterbrook, Devereux (2000) (Correct)
Generalised Unification of Temporal Logic Formulas - Hazelhurst (1999) (Correct)
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4: Symbolic boolean manipulation with ordered binary decision diagrams - Bryant - 1992
3: A Framework for Multi-Valued Reasoning over Inconsistent Viewpoints - Easterbrook, Chechik - 2000
3: A useful four-valued logic (context) - Belnap - 1977
BibTeX entry: (Update)
S Hazelhurst. `Generating and Model Checking a Hierarchy of Abstract Models'. Technical Report TRWits -CS-1999-0, Department of Computer Science, University of the Witwatersrand, (March 1999). http://citeseer.ist.psu.edu/hazelhurst99generating.html More
@misc{ hazelhurst99generating,
author = "S. Hazelhurst",
title = "Generating and Model Checking a Hierarchy of Abstract Models",
text = "S Hazelhurst. `Generating and Model Checking a Hierarchy of Abstract Models'.
Technical Report TRWits -CS-1999-0, Department of Computer Science, University
of the Witwatersrand, (March 1999).",
year = "1999",
url = "citeseer.ist.psu.edu/hazelhurst99generating.html" }
Citations (may not include all citations):183 A useful four-valued logic (context) - Belnap - 1977
178 Symbolic Model Checking for Sequential Circuit Verification - Burch, Clarke et al. - 1994
155 ACM Transactions on Programming Languages and Systems (context) - Clarke, Grumberg et al. - 1994
120 Bilattices and the Semantics of Logic Programming - Fitting - 1991
91 An Integration of Model Checking with Automated Proof Checki.. - Rajan, Shankar et al.
87 Verification of Arithmetic Functions with Binary Moment Diag.. - Bryant, Chen - 1994
67 ACM Transactions on Programming Languages and Systems (context) - Grumberg, Long et al. - 1994
54 Hybrid Decision Diagrams: Overcoming the Limitations of MTBD.. - Clarke, Fujita et al. - 1995
47 Formal Verification by Symbolic Evaluation of Partially-Orde.. - Seger, Bryant - 1995
37 Automatic Datapath Abstraction in Hardware Systems (context) - Hojati, Brayton
34 Formal Hardware Verification by Symbolic Ternary Trajectory .. (context) - Beatty, Bryant et al. - 1991
22 The Formal Verification of a Pipelined Double-Precision IEEE.. (context) - Aagaard, Seger - 1995
22 Lecture Notes in Computer Science (context) - Dill, CAV et al. - 1994
22 Lecture Notes in Computer Science (context) - Wolper, CAV et al. - 1995
20 Voss --- A Formal Hardware Verification System User's Guide (context) - Seger - 1993
20 Bilattices and modal operators - Ginsberg - 1990
19 Combining Model Checking and Theorem Proving to Verify Paral.. (context) - Hungar - 1993
15 A Simple Theorem Prover Based on Symbolic Trajectory Evaluat.. - Hazelhurst, Seger - 1995
14 A Methodology for Formal Hardware Verification with Applicat.. - Beatty - 1993
12 Compositional Model Checking of Partially-Ordered State Spac.. - Hazelhurst - 1996
5 Formal Verification of a 32-Bit Pipelined RISC Processor (context) - Darwish - 1994
4 Composing symbolic trajectory evaluation results (context) - Hazelhurst, Seger
4 Formal Hardware Verification: Methods and Systems in Compari.. (context) - Kropf - 1997
3 The Completeness of a Hardware Inference System (context) - Zhu, Seger
2 Model Checking Partially Ordered State Spaces - Hazelhurst, Seger - 1995
1 Formal Hardware Verification: Methods and Systems in Compari.. (context) - Hazelhurst, Seger
1 An integrated approach to verifying large circuits: A case s.. (context) - Hazelhurst, J-H - 1996
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Binary Decision Diagram Representations Of Firewall And .. - Hazelhurst, Fatti.. (1998) (Correct)
Compositional Model Checking Of Partially Ordered State Spaces - Hazelhurst (1996) (Correct)
A Simple Theorem Prover Based on Symbolic Trajectory.. - Hazelhurst, Seger (1993) (Correct)
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