See this document in CiteSeerX!

A Simple Theorem Prover Based on Symbolic Trajectory Evaluation and OBDDs (1993)  (Make Corrections)  (15 citations)
Scott Hazelhurst, Carl-Johan H. Seger
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems



  Home/Search   Context   Related

 
View or download:
cs.ubc.ca/pub/local/te...TR9341.ps.gz
cs.ubc.ca/ftp/local/te...TR9341.ps.gz
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  cs.wits.ac.za/~scott/ (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: Formalhardware verification based on symbolic trajectory evaluation shows considerable promise in verifying medium to large scale VLSI designs with a high degree of automation. However, in order to verify today's designs, a method for composing partial verification results is needed. One way of accomplishing this is to use a general purpose theorem prover to combine the verification results obtained by other tools. However, a specialised purpose theorem prover is more attractive since it can... (Update)

Context of citations to this paper:   More

...into the system. Alternatively, some researchers have augmented state space exploration tools with simple theorem proving capability [11, 1, 18]. We extend this approach with the integration of domain specific decision procedures. For example, to verify timing properties of a...

...into the system. Alternatively, some researchers have augmented state space exploration tools with simple theorem proving capability [25,1,7,40]. We follow the first approach. Designers can usually provide explanations for why they expect their designs to work; we seek to...

Cited by:   More
Exploiting Symmetry When Verifying Transistor-Level - Circuits By Symbolic   (Correct)
satGSTE: Combining the Abstraction of GSTE with the.. - Yang, Gil, Singerman   (Correct)
A Light-Weight Framework for Hardware Verification - Kern, Ono-Tesfaye, Greenstreet   (Correct)

Active bibliography (related documents):   More   All
1.2:   Compositional Model Checking Of Partially Ordered State Spaces - Hazelhurst (1996)   (Correct)
0.3:   Model Checking Partially Ordered State Spaces - Hazelhurst, Seger (1995)   (Correct)
0.3:   Verification of LOTOS Specifications using Term Rewriting.. - Kirkwood (1994)   (Correct)

Similar documents based on text:   More   All
0.4:   A Hybrid Verification Approach : Getting Deep into the.. - Hazelhurst, Weissberg.. (2002)   (Correct)
0.3:   Symbolic Trajectory Evaluation using a SAT solver - Claessen, Roorda   (Correct)
0.2:   Combining Theorem Proving and Trajectory Evaluation in an.. - Aagaard, Jones, Seger (1998)   (Correct)

Related documents from co-citation:   More   All
10:   Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories - Seger, Bryant - 1995
8:   Voss: A formal hardware verification system user's guide (context) - Seger - 1993
8:   Lecture Notes in Computer Science (context) - Book, Proc et al. - 1991

BibTeX entry:   (Update)

S. Hazelhurst and C.-J. H. Seger. A Simple Theorem Prover Based on Symbolic Trajectory Evaluation and OBDDs. Technical Report 93-41, Department of Computer Science, University of British Columbia, November 1993. Available by anonymous ftp as ftp://ftp.cs.ubc.ca/pub/local/techreports/1993/TR-93-41.ps.gz. http://citeseer.ist.psu.edu/hazelhurst93simple.html   More

@article{ hazelhurst95simple,
    author = "{S. Hazelhurst} and {C.-J.H. Seger}",
    title = "{A} {S}imple {T}heorem {P}rover {B}ased on {S}ymbolic {T}rajectory {E}valuation and {BDD}'s",
    journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
    volume = "14",
    number = "4",
    pages = "413--422",
    year = "1995",
    url = "citeseer.ist.psu.edu/hazelhurst93simple.html" }
Citations (may not include all citations):
1933   Communication and Concurrency (context) - Robin - 1989
1097   Automatic Verification of Finite-State Concurrent Systems Us.. (context) - Clarke, Emerson et al. - 1983
592   Introduction to HOL: a theorem proving environment for highe.. (context) - Gordon - 1993
510   Symbolic Boolean Manipulation with Ordered Binary-Decision D.. - Randal - 1992
334   A Computational Logic Handbook (context) - Boyer, Moore - 1988
295   PVS: A Prototype Verification System (context) - Owre, Rushby et al. - 1992
231   A Theory of Communicating Sequential Processes (context) - Brookes, Hoare et al. - 1984
187   HOL: A Proof Generating System for Higher-Order Logic (context) - Gordon - 1987
173   the Complexity of VLSI Implementations and Graph Representat.. - Randal, On - 1991
157   Edinburgh LCF : a mechanised logic of computation (context) - Gordon, Wadsworth et al. - 1979
128   Logic and computation : interactive proof with Cambridge LCF (context) - Paulson - 1987
121   Compositional Model Checking - Clarke, Long et al. - 1989
81   A Proposal for Standard ML (context) - Robin - 1984
73   The Concurrency Workbench (context) - Cleaveland, Parrow et al. - 1989
64   A Practical Decision Procedure for Arithmetic with Function .. (context) - Robert - 1979
47   Formal Verification by Symbolic Evaluation of Partially-Orde.. - Carl-Johan, Bryant et al. - 1993
43   Verifying Temporal Properties of Sequential Machines Without.. (context) - Coudert, Madre et al. - 1990
38   Analytica -- A Theorem Prover in Mathematica - Edmund, Xudong - 1992
38   and Compositional Verification (context) - David, July et al. - 1993
34   Formal Hardware Verification by Symbolic Ternary Trajectory .. (context) - Beatty, Bryant et al. - 1991
31   Multi-level Verification of Microprocessor-Based Systems (context) - Jeffrey - 1989
30   Linking BDD-based Symbolic Evaluation to Interactive Theorem.. (context) - Jeffrey, Seger - 1993
21   Extending the HOL Theorem Prover with a Computer Algebra Sys.. - Harrison, Thery - 1993
19   Combining Model Checking and Theorem Proving to Verify Paral.. (context) - Hardi - 1993
14   Formal Verification of Sequential Hardware: A Tutorial (context) - Michael - 1993
9   Automatic Reduction in CTL Compositional Model Checking (context) - Shiple, Chiodo et al. - 1992
7   A Proof Assistant for Symbolic Model-Checking (context) - Bradfield - 1992
7   Verification of a Multiplier: 64 Bits and Beyond (context) - Kurshan, Lamport - 1993
6   Verification of Parallel Systems via Decomposition - Groote, Moller - 1992
3   Verification Using Abstract Domains (context) - Michael - 1993
2   A Mathematically Precise Two-Level Hardware Verification Met.. (context) - Carl-Johan, Joyce et al. - 1992
1   Verification of the Tamarack-3 Microprocessor in a Hybrid Ve.. (context) - Computer, Verification et al. - 1993
1   Pages 229--240 of: Proceedings of the 1993 HOL Users' Group .. (context) - Anthony, of et al. - 1993
1   Deciding Combinations of Theories (context) - the, Computing et al. - 1984
1   Partial Specifications and Compositional Verification (context) - Kim, Bent - 1991



The graph only includes citing articles where the year of publication is known.


Documents on the same site (http://www.cs.wits.ac.za/~scott/):   More
Binary Decision Diagram Representations Of Firewall And .. - Hazelhurst, Fatti.. (1998)   (Correct)
Compositional Model Checking Of Partially Ordered State Spaces - Hazelhurst (1996)   (Correct)
Model Checking Partially Ordered State Spaces - Hazelhurst, Seger (1995)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC