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Abstract: Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purposecomputing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as... (Update)
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BibTeX entry: (Update)
J. R. Hauser and J. Wawrzynek, "Garp: A mips processor with a reconfigurable coprocessor," in IEEE Workshop on FPGAs for Custom Computing Machines, pp. 24--33, 1997. http://citeseer.ist.psu.edu/hauser97garp.html More
@inproceedings{ hauser97garp,
author = "John R. Hauser and John Wawrzynek",
title = "Garp: {A} {MIPS} Processor with a Reconfigurable Coprocessor",
booktitle = "{IEEE} Symposium on {FPGA}s for Custom Computing Machines",
publisher = "{IEEE} Computer Society Press",
address = "Los Alamitos, CA",
editor = "Kenneth L. Pocek and Jeffrey Arnold",
pages = "12--21",
year = "1997",
url = "citeseer.ist.psu.edu/hauser97garp.html" }
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