Ed Harcourt, Jon Mauney, Todd Cook  Home/Search
Context Related
| ncsu.edu/pub/tech/93/TR9318.ps.Z Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: ncsu.edu/research/techr...README (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: In modern instruction set processors, the temporal and concurrent properties of the instructions are often visible to the user of the processor. To use the processor as efficiently as possible, the user needs this information. Consequently, this instruction-level parallelism should be included in any behavioral processor specification. We present a technique for formally describing, at a high-level, the timing properties of pipelined, superscalar processors. We illustrate the technique by... (Update)
Context of citations to this paper: More
...guaranteed, or enormous cost is needed. Due to these limitations, analytical approaches are becoming more popular [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]. Many of these analytical studies, however, consider a simple machine model, thus largely ignoring the timing effects...
...approaches, analytical approaches are becoming more popular. There have been several recent studies about this issue [4, 8, 9, 18, 19, 20, 22, 23, 24, 27, 28]. In many of these studies, the assumed machine model is a simple non pipelined processor without cache memory [18, 22,...
Cited by: More
An Accurate Worst Case Timing Analysis Technique for RISC.. - Sung-Soo Lim (1994) (Correct)
An Accurate Worst Case Timing Analysis for RISC.. - Lim, Bae, Jang, Rhee.. (1995) (Correct)
Similar documents (at the sentence level):
7.6%: Formal Specification and Simulation of Instruction-Level.. - Harcourt, Mauney, Cook (1994) (Correct)
5.5%: From Processor Timing Specifications to Static Instruction .. - Harcourt, Mauney, Cook (1994) (Correct)
Active bibliography (related documents): More All
0.5: A Formal Verification of the Alternating Bit Protocol in the.. - Bezem, Groote (1993) (Correct)
0.5: Compilation and Synthesis for Real-Time Embedded Controllers - Fränzle, Müller-Olm (1999) (Correct)
0.2: How Fast Will the Flip Flop? - Mark Greenstreet And (Correct)
Similar documents based on text: More All
0.1: A Simple Mechanism for Improving the Accuracy and.. - Novack, Hummel, Nicolau (1995) (Correct)
0.0: Functional Specification and Simulation of Instruction Set.. - Ed Harcourt Jon (1994) (Correct)
0.0: Error Repair in Shift-Reduce Parsers - McKenzie, Yeatman, De Vere (1995) (Correct)
Related documents from co-citation: More All
2: A Real-Time Language with a Schedulability Analyzer (context) - Stoyenko - 1987
2: Aspects of Cache Memory and Instruction Buffer Performance (context) - Hill - 1987
2: A retargetable technique for predicting execution time - Harmon, Baker et al. - 1992
BibTeX entry: (Update)
E. Harcourt, J. Mauney, and T. Cook, "High-Level Timing Specification of Instruction-Level Parallel Processors," Tech. Rep. TR-93-18, Dept. of Computer Science, North Carolina State University, August 1993. http://citeseer.ist.psu.edu/harcourt93highlevel.html More
@techreport{ harcourt93high,
author = "Ed Harcourt and Jon Mauney and Todd Cook",
title = "High Level Timing Specification of Instruction-Level Parallel Processors",
number = "TR-93-18",
month = "24,",
year = "1993",
url = "citeseer.ist.psu.edu/harcourt93highlevel.html" }
Citations (may not include all citations):2732 Communicating Sequential Processes (context) - Hoare - 1985 ACM DBLP
1933 Communication and Concurrency (context) - Milner - 1989 ACM
1575 Computer Architecture: A Quantitative Approach (context) - Patterson, Hennessy - 1990 ACM
232 The Concurrency Workbench: A semantics-based tool for the ve.. - Cleaveland, Parrow et al. - 1993 DBLP
193 Superscalar Microprocessor Design (context) - Johnson - 1991
64 Calculi for synchrony and asynchrony (context) - Milner - 1983 DBLP
40 Elements of interaction (context) - Milner - 1993 ACM
25 The Edinburgh Concurrency Workbench (context) - Moller - 1992
24 CCS with priority choice (context) - Camilleri, Winskel - 1991
20 ACM Transactions on Programming Languages and Systems (context) - Milne, the et al. - 1985
19 Applications of Process Algebra (context) - Baeten - 1990 ACM
10 Information Processing Systems -- Open Systems Interconnecti.. (context) - Brinksma - 1988
8 Petri Nets: Applications and Relationships to Other Models o.. (context) - Brauer, Reisig et al. - 1987 ACM
5 System-level specification of instruction sets - Cook, Franzon et al. - 1993 DBLP
4 Current Trends in Hardware Verification and Automated Theore.. (context) - Birtwistle, Subrahmanyam - 1989 ACM
4 Theorem Provers in Circuit Design (context) - Stavridou, Melham et al. - 1992 ACM
2 Verification and Synthesis: Mathematical Aspects (context) - Leeser, Brown et al. - 1990
1 Formal Specification and Verifiation in VLSI Design (context) - Davie - 1990
1 Specification and simulation of instruction-level parallelis.. (context) - Harcourt, Mauney et al. - 1993
1 Functional semantics of microprocessors at the machine instr.. (context) - Paillet - 1990
1 A functional model of clocked microarchitectures (context) - Charlton, Jackson et al. - 1989 ACM DBLP
Documents on the same site (http://osl.csc.ncsu.edu/research/tech-reports/README.html): More
The Expected Size of the Sphere-of-Influence Graph - Dwyer (1995) (Correct)
Affordances for Acting in Direct Manipulation Interfaces - Amant (1998) (Correct)
HiPeR-l: A High Performance Reservation Protocol with.. - Sivaraman, Rouskas (1996) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC